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[PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro
From: |
Alistair Francis |
Subject: |
[PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro |
Date: |
Tue, 4 May 2021 08:13:24 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
---
target/riscv/translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a596f80f20..a1f794ffda 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,12 +67,6 @@ typedef struct DisasContext {
CPUState *cs;
} DisasContext;
-#ifdef TARGET_RISCV64
-#define CASE_OP_32_64(X) case X: case glue(X, W)
-#else
-#define CASE_OP_32_64(X) case X
-#endif
-
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
{
return ctx->misa & ext;
--
2.31.1
- [PULL 28/42] target/riscv: fix vrgather macro index variable type bug, (continued)
- [PULL 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/03
- [PULL 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/03
- [PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/03
- [PULL 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/03
- [PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/03
- [PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/03
- [PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro,
Alistair Francis <=
- [PULL 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/03
- [PULL 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/03
- [PULL 42/42] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/05/03
- Re: [PULL 00/42] riscv-to-apply queue, Peter Maydell, 2021/05/05