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[PULL v2 06/31] Hexagon (target/hexagon) TCG generation cleanup
From: |
Richard Henderson |
Subject: |
[PULL v2 06/31] Hexagon (target/hexagon) TCG generation cleanup |
Date: |
Sun, 2 May 2021 07:43:54 -0700 |
From: Taylor Simpson <tsimpson@quicinc.com>
Simplify TCG generation of hex_reg_written
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-2-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/genptr.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 7481f4c1dd..87f5d92994 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -35,7 +35,6 @@ static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
{
- TCGv one = tcg_const_tl(1);
TCGv zero = tcg_const_tl(0);
TCGv slot_mask = tcg_temp_new();
@@ -43,12 +42,17 @@ static inline void gen_log_predicated_reg_write(int rnum,
TCGv val, int slot)
tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
val, hex_new_value[rnum]);
#if HEX_DEBUG
- /* Do this so HELPER(debug_commit_end) will know */
- tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero,
- one, hex_reg_written[rnum]);
+ /*
+ * Do this so HELPER(debug_commit_end) will know
+ *
+ * Note that slot_mask indicates the value is not written
+ * (i.e., slot was cancelled), so we create a true/false value before
+ * or'ing with hex_reg_written[rnum].
+ */
+ tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
+ tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
#endif
- tcg_temp_free(one);
tcg_temp_free(zero);
tcg_temp_free(slot_mask);
}
--
2.25.1
- [PULL v2 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair, (continued)
- [PULL v2 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair, Richard Henderson, 2021/05/02
- [PULL v2 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM, Richard Henderson, 2021/05/02
- [PULL v2 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu, Richard Henderson, 2021/05/02
- [PULL v2 05/31] target/hexagon: remove unnecessary semicolons, Richard Henderson, 2021/05/02
- [PULL v2 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time, Richard Henderson, 2021/05/02
- [PULL v2 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN, Richard Henderson, 2021/05/02
- [PULL v2 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function, Richard Henderson, 2021/05/02
- [PULL v2 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes, Richard Henderson, 2021/05/02
- [PULL v2 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess, Richard Henderson, 2021/05/02
- [PULL v2 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition, Richard Henderson, 2021/05/02
- [PULL v2 06/31] Hexagon (target/hexagon) TCG generation cleanup,
Richard Henderson <=
- [PULL v2 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn, Richard Henderson, 2021/05/02
- [PULL v2 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh), Richard Henderson, 2021/05/02
- [PULL v2 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h, Richard Henderson, 2021/05/02
- [PULL v2 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate, Richard Henderson, 2021/05/02
- [PULL v2 21/31] Hexagon (target/hexagon) compile all debug code, Richard Henderson, 2021/05/02
- [PULL v2 22/31] Hexagon (target/hexagon) add F2_sfrecipa instruction, Richard Henderson, 2021/05/02
- [PULL v2 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c, Richard Henderson, 2021/05/02
- [PULL v2 28/31] Hexagon (target/hexagon) bit reverse (brev) addressing, Richard Henderson, 2021/05/02
- [PULL v2 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics, Richard Henderson, 2021/05/02
- [PULL v2 23/31] Hexagon (target/hexagon) add F2_sfinvsqrta, Richard Henderson, 2021/05/02