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[PULL v2 00/31] target/hexagon patch queue
From: |
Richard Henderson |
Subject: |
[PULL v2 00/31] target/hexagon patch queue |
Date: |
Sun, 2 May 2021 07:43:48 -0700 |
The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into
staging (2021-04-30 16:02:00 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-hex-20210502
for you to fetch changes up to e628c0156be74dd14a261bbd18674bacd1afcc7d:
Hexagon (target/hexagon) CABAC decode bin (2021-05-01 16:06:11 -0700)
----------------------------------------------------------------
Minor cleanups.
Finish the rest of the hexagon integer instructions.
----------------------------------------------------------------
Taylor Simpson (31):
target/hexagon: translation changes
target/hexagon: remove unnecessary checks in find_iclass_slots
target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM
target/hexagon: fix typo in comment
target/hexagon: remove unnecessary semicolons
Hexagon (target/hexagon) TCG generation cleanup
Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair
Hexagon (target/hexagon) remove unnecessary inline directives
Hexagon (target/hexagon) use env_archcpu and env_cpu
Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN
Hexagon (target/hexagon) decide if pred has been written at TCG gen time
Hexagon (target/hexagon) change variables from int to bool when
appropriate
Hexagon (target/hexagon) remove unused carry_from_add64 function
Hexagon (target/hexagon) change type of softfloat_roundingmodes
Hexagon (target/hexagon) use softfloat default NaN and tininess
Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn
Hexagon (target/hexagon) use softfloat for float-to-int conversions
Hexagon (target/hexagon) cleanup ternary operators in semantics
Hexagon (target/hexagon) cleanup reg_field_info definition
Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h
Hexagon (target/hexagon) compile all debug code
Hexagon (target/hexagon) add F2_sfrecipa instruction
Hexagon (target/hexagon) add F2_sfinvsqrta
Hexagon (target/hexagon) add A5_ACS (vacsh)
Hexagon (target/hexagon) add A6_vminub_RdP
Hexagon (target/hexagon) add A4_addp_c/A4_subp_c
Hexagon (target/hexagon) circular addressing
Hexagon (target/hexagon) bit reverse (brev) addressing
Hexagon (target/hexagon) load and unpack bytes instructions
Hexagon (target/hexagon) load into shifted register instructions
Hexagon (target/hexagon) CABAC decode bin
target/hexagon/arch.h | 9 +-
target/hexagon/conv_emu.h | 31 ---
target/hexagon/cpu.h | 5 -
target/hexagon/cpu_bits.h | 2 +-
target/hexagon/gen_tcg.h | 424 ++++++++++++++++++++++++++++-
target/hexagon/helper.h | 23 +-
target/hexagon/insn.h | 21 +-
target/hexagon/internal.h | 11 +-
target/hexagon/macros.h | 118 ++++++++-
target/hexagon/reg_fields.h | 4 +-
target/hexagon/translate.h | 9 +-
linux-user/hexagon/cpu_loop.c | 2 +-
target/hexagon/arch.c | 181 ++++++++++---
target/hexagon/conv_emu.c | 177 -------------
target/hexagon/cpu.c | 14 +-
target/hexagon/decode.c | 84 +++---
target/hexagon/fma_emu.c | 40 +--
target/hexagon/genptr.c | 233 +++++++++++++---
target/hexagon/iclass.c | 4 -
target/hexagon/op_helper.c | 398 ++++++++++++++++++----------
target/hexagon/reg_fields.c | 3 +-
target/hexagon/translate.c | 175 ++++++------
tests/tcg/hexagon/brev.c | 190 +++++++++++++
tests/tcg/hexagon/circ.c | 486 ++++++++++++++++++++++++++++++++++
tests/tcg/hexagon/fpstuff.c | 242 +++++++++++++++++
tests/tcg/hexagon/load_align.c | 415 +++++++++++++++++++++++++++++
tests/tcg/hexagon/load_unpack.c | 474 +++++++++++++++++++++++++++++++++
tests/tcg/hexagon/misc.c | 47 ++++
tests/tcg/hexagon/multi_result.c | 282 ++++++++++++++++++++
fpu/softfloat-specialize.c.inc | 3 +
target/hexagon/gen_tcg_funcs.py | 2 +-
target/hexagon/imported/alu.idef | 44 +++
target/hexagon/imported/compare.idef | 12 +-
target/hexagon/imported/encode_pp.def | 30 +++
target/hexagon/imported/float.idef | 32 +++
target/hexagon/imported/ldst.idef | 68 +++++
target/hexagon/imported/macros.def | 47 ++++
target/hexagon/imported/shift.idef | 47 ++++
target/hexagon/meson.build | 1 -
tests/tcg/hexagon/Makefile.target | 6 +
40 files changed, 3757 insertions(+), 639 deletions(-)
delete mode 100644 target/hexagon/conv_emu.h
delete mode 100644 target/hexagon/conv_emu.c
create mode 100644 tests/tcg/hexagon/brev.c
create mode 100644 tests/tcg/hexagon/circ.c
create mode 100644 tests/tcg/hexagon/load_align.c
create mode 100644 tests/tcg/hexagon/load_unpack.c
create mode 100644 tests/tcg/hexagon/multi_result.c
- [PULL v2 00/31] target/hexagon patch queue,
Richard Henderson <=
- [PULL v2 01/31] target/hexagon: translation changes, Richard Henderson, 2021/05/02
- [PULL v2 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots, Richard Henderson, 2021/05/02
- [PULL v2 04/31] target/hexagon: fix typo in comment, Richard Henderson, 2021/05/02
- [PULL v2 08/31] Hexagon (target/hexagon) remove unnecessary inline directives, Richard Henderson, 2021/05/02
- [PULL v2 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair, Richard Henderson, 2021/05/02
- [PULL v2 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM, Richard Henderson, 2021/05/02
- [PULL v2 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu, Richard Henderson, 2021/05/02
- [PULL v2 05/31] target/hexagon: remove unnecessary semicolons, Richard Henderson, 2021/05/02
- [PULL v2 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time, Richard Henderson, 2021/05/02
- [PULL v2 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN, Richard Henderson, 2021/05/02