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[PATCH v6 13/82] target/arm: Implement SVE2 integer multiply long
From: |
Richard Henderson |
Subject: |
[PATCH v6 13/82] target/arm: Implement SVE2 integer multiply long |
Date: |
Fri, 30 Apr 2021 13:25:01 -0700 |
Exclude PMULL from this category for the moment.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sve.h | 15 +++++++++++++++
target/arm/sve.decode | 9 +++++++++
target/arm/sve_helper.c | 31 +++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 9 +++++++++
4 files changed, 64 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 3286a9c205..ad8121eec6 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2347,4 +2347,19 @@ DEF_HELPER_FLAGS_6(sve_stdd_le_zd_mte, TCG_CALL_NO_WG,
DEF_HELPER_FLAGS_6(sve_stdd_be_zd_mte, TCG_CALL_NO_WG,
void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_4(sve2_sqdmull_zzz_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqdmull_zzz_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqdmull_zzz_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_smull_zzz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_smull_zzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_smull_zzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_umull_zzz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_umull_zzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_umull_zzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index f6f21426ef..d9a72b7661 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1196,3 +1196,12 @@ SSUBWB 01000101 .. 0 ..... 010 100 ..... .....
@rd_rn_rm
SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm
USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm
USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm
+
+## SVE2 integer multiply long
+
+SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm
+SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm
+SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm
+SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm
+UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm
+UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index cf0dbb3987..f30f3722af 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1154,6 +1154,37 @@ DO_ZZZ_TB(sve2_uabdl_h, uint16_t, uint8_t, H1_2, H1,
DO_ABD)
DO_ZZZ_TB(sve2_uabdl_s, uint32_t, uint16_t, H1_4, H1_2, DO_ABD)
DO_ZZZ_TB(sve2_uabdl_d, uint64_t, uint32_t, , H1_4, DO_ABD)
+DO_ZZZ_TB(sve2_smull_zzz_h, int16_t, int8_t, H1_2, H1, DO_MUL)
+DO_ZZZ_TB(sve2_smull_zzz_s, int32_t, int16_t, H1_4, H1_2, DO_MUL)
+DO_ZZZ_TB(sve2_smull_zzz_d, int64_t, int32_t, , H1_4, DO_MUL)
+
+DO_ZZZ_TB(sve2_umull_zzz_h, uint16_t, uint8_t, H1_2, H1, DO_MUL)
+DO_ZZZ_TB(sve2_umull_zzz_s, uint32_t, uint16_t, H1_4, H1_2, DO_MUL)
+DO_ZZZ_TB(sve2_umull_zzz_d, uint64_t, uint32_t, , H1_4, DO_MUL)
+
+/* Note that the multiply cannot overflow, but the doubling can. */
+static inline int16_t do_sqdmull_h(int16_t n, int16_t m)
+{
+ int16_t val = n * m;
+ return DO_SQADD_H(val, val);
+}
+
+static inline int32_t do_sqdmull_s(int32_t n, int32_t m)
+{
+ int32_t val = n * m;
+ return DO_SQADD_S(val, val);
+}
+
+static inline int64_t do_sqdmull_d(int64_t n, int64_t m)
+{
+ int64_t val = n * m;
+ return do_sqadd_d(val, val);
+}
+
+DO_ZZZ_TB(sve2_sqdmull_zzz_h, int16_t, int8_t, H1_2, H1, do_sqdmull_h)
+DO_ZZZ_TB(sve2_sqdmull_zzz_s, int32_t, int16_t, H1_4, H1_2, do_sqdmull_s)
+DO_ZZZ_TB(sve2_sqdmull_zzz_d, int64_t, int32_t, , H1_4, do_sqdmull_d)
+
#undef DO_ZZZ_TB
#define DO_ZZZ_WTB(NAME, TYPEW, TYPEN, HW, HN, OP) \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 70900c122f..19a1f289d8 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6021,6 +6021,15 @@ DO_SVE2_ZZZ_TB(SADDLBT, saddl, false, true)
DO_SVE2_ZZZ_TB(SSUBLBT, ssubl, false, true)
DO_SVE2_ZZZ_TB(SSUBLTB, ssubl, true, false)
+DO_SVE2_ZZZ_TB(SQDMULLB_zzz, sqdmull_zzz, false, false)
+DO_SVE2_ZZZ_TB(SQDMULLT_zzz, sqdmull_zzz, true, true)
+
+DO_SVE2_ZZZ_TB(SMULLB_zzz, smull_zzz, false, false)
+DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true)
+
+DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false)
+DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true)
+
#define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \
static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
{ \
--
2.25.1
- [PATCH v6 12/82] target/arm: Implement SVE2 integer add/subtract wide, (continued)
- [PATCH v6 12/82] target/arm: Implement SVE2 integer add/subtract wide, Richard Henderson, 2021/04/30
- [PATCH v6 11/82] target/arm: Implement SVE2 integer add/subtract interleaved long, Richard Henderson, 2021/04/30
- [PATCH v6 14/82] target/arm: Implement PMULLB and PMULLT, Richard Henderson, 2021/04/30
- [PATCH v6 15/82] target/arm: Implement SVE2 bitwise shift left long, Richard Henderson, 2021/04/30
- [PATCH v6 17/82] target/arm: Implement SVE2 bitwise permute, Richard Henderson, 2021/04/30
- [PATCH v6 23/82] target/arm: Implement SVE2 integer absolute difference and accumulate, Richard Henderson, 2021/04/30
- [PATCH v6 18/82] target/arm: Implement SVE2 complex integer add, Richard Henderson, 2021/04/30
- [PATCH v6 16/82] target/arm: Implement SVE2 bitwise exclusive-or interleaved, Richard Henderson, 2021/04/30
- [PATCH v6 22/82] target/arm: Implement SVE2 bitwise shift and insert, Richard Henderson, 2021/04/30
- [PATCH v6 21/82] target/arm: Implement SVE2 bitwise shift right and accumulate, Richard Henderson, 2021/04/30
- [PATCH v6 13/82] target/arm: Implement SVE2 integer multiply long,
Richard Henderson <=
- [PATCH v6 24/82] target/arm: Implement SVE2 saturating extract narrow, Richard Henderson, 2021/04/30
- [PATCH v6 25/82] target/arm: Implement SVE2 floating-point pairwise, Richard Henderson, 2021/04/30
- [PATCH v6 28/82] target/arm: Implement SVE2 UQSHRN, UQRSHRN, Richard Henderson, 2021/04/30
- [PATCH v6 20/82] target/arm: Implement SVE2 integer add/subtract long with carry, Richard Henderson, 2021/04/30
- [PATCH v6 19/82] target/arm: Implement SVE2 integer absolute difference and accumulate long, Richard Henderson, 2021/04/30
- [PATCH v6 26/82] target/arm: Implement SVE2 SHRN, RSHRN, Richard Henderson, 2021/04/30
- [PATCH v6 30/82] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS, Richard Henderson, 2021/04/30
- [PATCH v6 29/82] target/arm: Implement SVE2 SQSHRN, SQRSHRN, Richard Henderson, 2021/04/30
- [PATCH v6 32/82] target/arm: Implement SVE2 bitwise ternary operations, Richard Henderson, 2021/04/30
- [PATCH v6 31/82] target/arm: Implement SVE2 WHILERW, WHILEWR, Richard Henderson, 2021/04/30