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[RESEND PATCH 09/32] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
From: |
Yang Zhong |
Subject: |
[RESEND PATCH 09/32] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX |
Date: |
Fri, 30 Apr 2021 14:24:32 +0800 |
From: Sean Christopherson <sean.j.christopherson@intel.com>
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the enclave has has been initialized by EINIT. Cannot
be set by software, i.e. forced to zero in CPUID.
- DEBUG: permits a debugger to read/write into the enclave.
- MODE64BIT: the enclave runs in 64-bit mode
- PROVISIONKEY: grants has access to the provision key
- EINITTOKENKEY: grants access to the EINIT token key, i.e. the
enclave can generate EINIT tokens
- KSS: Key Separation and Sharing enabled for the enclave.
Note that the entirety of CPUID.0x12.0x1, i.e. all registers, enumerates
the allowed ATTRIBUTES (128 bits), but only bits 31:0 are directly
exposed to the user (via FEAT_12_1_EAX). Bits 63:32 are currently all
reserved and bits 127:64 correspond to the allowed XSAVE Feature Request
Mask, which is calculated based on other CPU features, e.g. XSAVE, MPX,
AVX, etc... and is not exposed to the user.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
target/i386/cpu.c | 21 +++++++++++++++++++++
target/i386/cpu.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e723f52e22..ec12e12a33 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -678,6 +678,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t
vendor1,
#define TCG_14_0_ECX_FEATURES 0
#define TCG_SGX_12_0_EAX_FEATURES 0
#define TCG_SGX_12_0_EBX_FEATURES 0
+#define TCG_SGX_12_1_EAX_FEATURES 0
typedef enum FeatureWordType {
CPUID_FEATURE_WORD,
@@ -1366,6 +1367,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]
= {
},
.tcg_features = TCG_SGX_12_0_EBX_FEATURES,
},
+
+ [FEAT_SGX_12_1_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, "sgx-debug", "sgx-mode64", NULL,
+ "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x12,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
+ },
};
typedef struct FeatureMask {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a3c91d5848..9df748119f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -551,6 +551,7 @@ typedef enum FeatureWord {
FEAT_14_0_ECX,
FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
+ FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
FEATURE_WORDS,
} FeatureWord;
--
2.29.2.334.gfaefdd61ec
- [RESEND PATCH 01/32] memory: Add RAM_PROTECTED flag to skip IOMMU mappings, (continued)
- [RESEND PATCH 01/32] memory: Add RAM_PROTECTED flag to skip IOMMU mappings, Yang Zhong, 2021/04/30
- [RESEND PATCH 03/32] qom: Add memory-backend-epc ObjectOptions support, Yang Zhong, 2021/04/30
- [RESEND PATCH 08/32] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX, Yang Zhong, 2021/04/30
- [RESEND PATCH 04/32] i386: Add 'sgx-epc' device to expose EPC sections to guest, Yang Zhong, 2021/04/30
- [RESEND PATCH 06/32] i386: Add primary SGX CPUID and MSR defines, Yang Zhong, 2021/04/30
- [RESEND PATCH 05/32] vl: Add "sgx-epc" option to expose SGX EPC sections to guest, Yang Zhong, 2021/04/30
- [RESEND PATCH 11/32] i386: Add feature control MSR dependency when SGX is enabled, Yang Zhong, 2021/04/30
- [RESEND PATCH 13/32] linux-headers: Add placeholder for KVM_CAP_SGX_ATTRIBUTE, Yang Zhong, 2021/04/30
- [RESEND PATCH 12/32] i386: Update SGX CPUID info according to hardware/KVM/user input, Yang Zhong, 2021/04/30
- [RESEND PATCH 07/32] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX, Yang Zhong, 2021/04/30
- [RESEND PATCH 09/32] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX,
Yang Zhong <=
- [RESEND PATCH 10/32] i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs, Yang Zhong, 2021/04/30
- [RESEND PATCH 14/32] i386: kvm: Add support for exposing PROVISIONKEY to guest, Yang Zhong, 2021/04/30
- [RESEND PATCH 15/32] i386: Propagate SGX CPUID sub-leafs to KVM, Yang Zhong, 2021/04/30
- [RESEND PATCH 17/32] hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly, Yang Zhong, 2021/04/30
- [RESEND PATCH 16/32] Adjust min CPUID level to 0x12 when SGX is enabled, Yang Zhong, 2021/04/30
- [RESEND PATCH 18/32] hw/i386/pc: Account for SGX EPC sections when calculating device memory, Yang Zhong, 2021/04/30
- [RESEND PATCH 19/32] i386/pc: Add e820 entry for SGX EPC section(s), Yang Zhong, 2021/04/30
- [RESEND PATCH 20/32] i386: acpi: Add SGX EPC entry to ACPI tables, Yang Zhong, 2021/04/30
- [RESEND PATCH 21/32] q35: Add support for SGX EPC, Yang Zhong, 2021/04/30
- [RESEND PATCH 22/32] i440fx: Add support for SGX EPC, Yang Zhong, 2021/04/30