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[PATCH v3 00/30] Base for adding PowerPC 64-bit instructions
From: |
Richard Henderson |
Subject: |
[PATCH v3 00/30] Base for adding PowerPC 64-bit instructions |
Date: |
Thu, 29 Apr 2021 18:15:13 -0700 |
Changes for v3:
* More changes for decodetree.
* Cleanup exception/is_jmp logic to the point exception is removed.
* Fold in Luis' isa check for prefixed insn support.
* Share trans_* between prefixed and non-prefixed instructions.
* Use macros to minimize the trans_* boilerplate.
* Fix decode mistake for STHX/STHXU.
r~
Luis Fernando Fujita Pires (1):
decodetree: Add support for 64-bit instructions
Richard Henderson (29):
decodetree: Introduce whex and whexC helpers
decodetree: More use of f-strings
decodetree: Extend argument set syntax to allow types
target/ppc: Add cia field to DisasContext
target/ppc: Split out decode_legacy
target/ppc: Move DISAS_NORETURN setting into gen_exception*
target/ppc: Remove special case for POWERPC_SYSCALL
target/ppc: Remove special case for POWERPC_EXCP_TRAP
target/ppc: Simplify gen_debug_exception
target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE}
target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT
target/ppc: Remove unnecessary gen_io_end calls
target/ppc: Introduce gen_icount_io_start
target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN
target/ppc: Remove DisasContext.exception
target/ppc: Move single-step check to ppc_tr_tb_stop
target/ppc: Tidy exception vs exit_tb
target/ppc: Mark helper_raise_exception* as noreturn
target/ppc: Use translator_loop_temp_check
target/ppc: Introduce macros to check isa extensions
target/ppc: Add infrastructure for prefixed insns
target/ppc: Move page crossing check to ppc_tr_translate_insn
target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
target/ppc: Implement PNOP
target/ppc: Move D/DS/X-form integer loads to decodetree
target/ppc: Implement prefixed integer load instructions
target/ppc: Move D/DS/X-form integer stores to decodetree
target/ppc: Implement prefixed integer store instructions
docs/devel/decodetree.rst | 11 +-
target/ppc/cpu.h | 5 +-
target/ppc/helper.h | 4 +-
target/ppc/insn32.decode | 91 +++
target/ppc/insn64.decode | 71 +++
tests/decode/succ_argset_type1.decode | 1 +
linux-user/ppc/cpu_loop.c | 6 -
target/ppc/translate.c | 672 +++++++++------------
target/ppc/translate/fixedpoint-impl.c.inc | 200 ++++++
target/ppc/translate_init.c.inc | 143 +----
scripts/decodetree.py | 172 +++---
target/ppc/meson.build | 9 +
12 files changed, 772 insertions(+), 613 deletions(-)
create mode 100644 target/ppc/insn32.decode
create mode 100644 target/ppc/insn64.decode
create mode 100644 tests/decode/succ_argset_type1.decode
create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
--
2.25.1
- [PATCH v3 00/30] Base for adding PowerPC 64-bit instructions,
Richard Henderson <=
- [PATCH v3 01/30] decodetree: Introduce whex and whexC helpers, Richard Henderson, 2021/04/29
- [PATCH v3 04/30] decodetree: Extend argument set syntax to allow types, Richard Henderson, 2021/04/29
- [PATCH v3 05/30] target/ppc: Add cia field to DisasContext, Richard Henderson, 2021/04/29
- [PATCH v3 03/30] decodetree: Add support for 64-bit instructions, Richard Henderson, 2021/04/29
- [PATCH v3 02/30] decodetree: More use of f-strings, Richard Henderson, 2021/04/29