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Re: [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions |
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Date: |
Tue, 27 Apr 2021 16:06:33 +1000 |
On Wed, Apr 21, 2021 at 2:20 PM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index d64326fd864..938c23088eb 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -598,6 +598,8 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> clz 011000 000000 ..... 001 ..... 0010011 @r2
> ctz 011000 000001 ..... 001 ..... 0010011 @r2
> cpop 011000 000010 ..... 001 ..... 0010011 @r2
> +sext_b 011000 000100 ..... 001 ..... 0010011 @r2
> +sext_h 011000 000101 ..... 001 ..... 0010011 @r2
>
> andn 0100000 .......... 111 ..... 0110011 @r
> orn 0100000 .......... 110 ..... 0110011 @r
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 2aa4515fe31..1496996a660 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -95,6 +95,18 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
> return gen_arith(ctx, a, tcg_gen_umax_tl);
> }
>
> +static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, tcg_gen_ext8s_tl);
> +}
> +
> +static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, tcg_gen_ext16s_tl);
> +}
> +
> /* RV64-only instructions */
> #ifdef TARGET_RISCV64
>
> --
> 2.17.1
>
>
- [PATCH v5 04/17] target/riscv: rvb: logic-with-negate, (continued)
- [PATCH v5 04/17] target/riscv: rvb: logic-with-negate, frank . chang, 2021/04/21
- [PATCH v5 03/17] target/riscv: rvb: count bits set, frank . chang, 2021/04/21
- [PATCH v5 05/17] target/riscv: rvb: pack two words into one register, frank . chang, 2021/04/21
- [PATCH v5 06/17] target/riscv: rvb: min/max instructions, frank . chang, 2021/04/21
- [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, frank . chang, 2021/04/21
- [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions, frank . chang, 2021/04/21
- Re: [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions,
Alistair Francis <=
- [PATCH v5 09/17] target/riscv: rvb: single-bit instructions, frank . chang, 2021/04/21
- [PATCH v5 10/17] target/riscv: rvb: shift ones, frank . chang, 2021/04/21
- [PATCH v5 11/17] target/riscv: rvb: rotate (left/right), frank . chang, 2021/04/21
- [PATCH v5 12/17] target/riscv: rvb: generalized reverse, frank . chang, 2021/04/21
- [PATCH v5 13/17] target/riscv: rvb: generalized or-combine, frank . chang, 2021/04/21
- [PATCH v5 14/17] target/riscv: rvb: address calculation, frank . chang, 2021/04/21
- [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend, frank . chang, 2021/04/21
- [PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line, frank . chang, 2021/04/21
- [PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option, frank . chang, 2021/04/21