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[PATCH v5 cxl2.0-v3-doe 2/6] include/hw/pci: headers for PCIe DOE
From: |
Chris Browy |
Subject: |
[PATCH v5 cxl2.0-v3-doe 2/6] include/hw/pci: headers for PCIe DOE |
Date: |
Mon, 26 Apr 2021 13:16:43 -0400 |
From: hchkuo <hchkuo@avery-design.com.tw>
Macros for the vender ID of PCI-SIG and the size of PCIe Data Object
Exchange.
Signed-off-by: Chris Browy <cbrowy@avery-design.com>
---
include/hw/pci/pci_ids.h | 2 ++
include/hw/pci/pcie_regs.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index 95f92d98e9..471c915395 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -157,6 +157,8 @@
/* Vendors and devices. Sort key: vendor first, device next. */
+#define PCI_VENDOR_ID_PCI_SIG 0x0001
+
#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
#define PCI_DEVICE_ID_LSI_53C810 0x0001
#define PCI_DEVICE_ID_LSI_53C895A 0x0012
diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h
index 1db86b0ec4..5ec7014211 100644
--- a/include/hw/pci/pcie_regs.h
+++ b/include/hw/pci/pcie_regs.h
@@ -179,4 +179,7 @@ typedef enum PCIExpLinkWidth {
#define PCI_ACS_VER 0x1
#define PCI_ACS_SIZEOF 8
+/* DOE Capability Register Fields */
+#define PCI_DOE_SIZEOF 24
+
#endif /* QEMU_PCIE_REGS_H */
--
2.17.1
- [PATCH v5 cxl2.0-v3-doe 0/6] QEMU PCIe DOE for PCIe 4.0/5.0 and CXL 2.0, Chris Browy, 2021/04/26
- [PATCH v5 cxl2.0-v3-doe 1/6] standard-headers/linux/pci_regs: PCI header from Linux kernel, Chris Browy, 2021/04/26
- [PATCH v5 cxl2.0-v3-doe 2/6] include/hw/pci: headers for PCIe DOE,
Chris Browy <=
- [PATCH v5 cxl2.0-v3-doe 3/6] hw/pci: PCIe Data Object Exchange implementation, Chris Browy, 2021/04/26
- [PATCH v5 cxl2.0-v3-doe 4/6] cxl/compliance: CXL Compliance Data Object Exchange implementation, Chris Browy, 2021/04/26
- [PATCH v5 cxl2.0-v3-doe 5/6] cxl/cdat: CXL CDAT Data Object Exchange implementation, Chris Browy, 2021/04/26
- [PATCH v5 cxl2.0-v3-doe 6/6] test/cdat: CXL CDAT test data, Chris Browy, 2021/04/26