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Re: [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)


From: Richard Henderson
Subject: Re: [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
Date: Tue, 20 Apr 2021 18:29:10 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1

On 4/20/21 10:54 AM, Philippe Mathieu-Daudé wrote:
The CACHEE opcode "requires CP0 privilege".

The pseudocode checks in the ISA manual is:

     if is_eva and not C0.Config5.EVA:
       raise exception('RI')

     if not IsCoprocessor0Enabled():
       raise coprocessor_exception(0)

Add the missing checks.

Inspired-by: Richard Henderson<richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
---
  target/mips/translate.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~




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