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[RFC v14 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features retu
From: |
Claudio Fontana |
Subject: |
[RFC v14 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool |
Date: |
Fri, 16 Apr 2021 18:28:06 +0200 |
return false on error, true on success.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-sve.h | 2 +-
target/arm/cpu-sve.c | 17 +++++++++--------
target/arm/cpu.c | 3 +--
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h
index ece36d2a0c..6ab74b1d8f 100644
--- a/target/arm/cpu-sve.h
+++ b/target/arm/cpu-sve.h
@@ -26,7 +26,7 @@
#include "cpu.h"
/* called by arm_cpu_finalize_features in realizefn */
-void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp);
+bool cpu_sve_finalize_features(ARMCPU *cpu, Error **errp);
/* add the CPU SVE properties */
void cpu_sve_add_props(Object *obj);
diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c
index 5190e4a639..24bffbba8b 100644
--- a/target/arm/cpu-sve.c
+++ b/target/arm/cpu-sve.c
@@ -49,7 +49,7 @@ static bool apply_max_vq(unsigned long *sve_vq_map, unsigned
long *sve_vq_init,
return true;
}
-void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
+bool cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
{
/*
* If any vector lengths are explicitly enabled with sve<N> properties,
@@ -86,7 +86,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
"length, sve-max-vq=%d (%d bits)\n",
max_vq * 128, cpu->sve_max_vq,
cpu->sve_max_vq * 128);
- return;
+ return false;
}
if (kvm_enabled()) {
kvm_sve_enable_lens(cpu->sve_vq_map, cpu->sve_vq_init, max_vq,
@@ -98,7 +98,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
/* No explicit bits enabled, and no implicit bits from sve-max-vq. */
if (!cpu_isar_feature(aa64_sve, cpu)) {
/* SVE is disabled and so are all vector lengths. Good. */
- return;
+ return true;
}
if (kvm_enabled()) {
max_vq = kvm_sve_disable_lens(cpu->sve_vq_map, cpu->sve_vq_init,
@@ -108,7 +108,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
errp);
}
if (!max_vq) {
- return;
+ return false;
}
max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
}
@@ -122,7 +122,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
max_vq = cpu->sve_max_vq;
if (!apply_max_vq(cpu->sve_vq_map, cpu->sve_vq_init, max_vq,
errp)) {
- return;
+ return false;
}
}
/*
@@ -136,11 +136,11 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
if (kvm_enabled()) {
if (!kvm_sve_validate_lens(cpu->sve_vq_map, max_vq, kvm_supported,
errp, cpu->sve_max_vq)) {
- return;
+ return false;
}
} else if (tcg_enabled()) {
if (!tcg_sve_validate_lens(cpu->sve_vq_map, max_vq, errp)) {
- return;
+ return false;
}
}
@@ -153,11 +153,12 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
error_append_hint(errp, "SVE must be enabled to enable vector "
"lengths.\n");
error_append_hint(errp, "Add sve=on to the CPU property list.\n");
- return;
+ return false;
}
/* From now on sve_max_vq is the actual maximum supported length. */
cpu->sve_max_vq = max_vq;
+ return true;
}
static void get_prop_max_vq(Object *obj, Visitor *v, const char *name,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index be5d857e65..d192dd1ba4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -821,8 +821,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
#ifdef TARGET_AARCH64
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- cpu_sve_finalize_features(cpu, &local_err);
- if (local_err != NULL) {
+ if (!cpu_sve_finalize_features(cpu, &local_err)) {
error_propagate(errp, local_err);
return;
}
--
2.26.2
- [RFC v14 46/80] target/arm: cleanup cpu includes, (continued)
- [RFC v14 46/80] target/arm: cleanup cpu includes, Claudio Fontana, 2021/04/16
- [RFC v14 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/04/16
- [RFC v14 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds, Claudio Fontana, 2021/04/16
- [RFC v14 54/80] Revert "target/arm: Restrict v8M IDAU to TCG", Claudio Fontana, 2021/04/16
- [RFC v14 52/80] tests: device-introspect-test: cope with ARM TCG-only devices, Claudio Fontana, 2021/04/16
- [RFC v14 55/80] target/arm: create kvm cpu accel class, Claudio Fontana, 2021/04/16
- [RFC v14 51/80] tests: do not run test-hmp on all machines for ARM KVM-only, Claudio Fontana, 2021/04/16
- [RFC v14 57/80] target/arm: add tcg cpu accel class, Claudio Fontana, 2021/04/16
- [RFC v14 58/80] target/arm: move TCG gt timer creation code in tcg/, Claudio Fontana, 2021/04/16
- [RFC v14 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64, Claudio Fontana, 2021/04/16
- [RFC v14 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool,
Claudio Fontana <=
- [RFC v14 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64, Claudio Fontana, 2021/04/16
- [RFC v14 60/80] target/arm: cpu-sve: rename functions according to module prefix, Claudio Fontana, 2021/04/16
- [RFC v14 56/80] target/arm: move kvm post init initialization to kvm cpu accel, Claudio Fontana, 2021/04/16
- [RFC v14 61/80] target/arm: cpu-sve: split TCG and KVM functionality, Claudio Fontana, 2021/04/16
- [RFC v14 59/80] target/arm: cpu-sve: new module, Claudio Fontana, 2021/04/16
- [RFC v14 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64, Claudio Fontana, 2021/04/16
- [RFC v14 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64, Claudio Fontana, 2021/04/16
- [RFC v14 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el, Claudio Fontana, 2021/04/16
- [RFC v14 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules, Claudio Fontana, 2021/04/16
- [RFC v14 72/80] target/arm: cpu-common: wrap a64-only check with is_a64, Claudio Fontana, 2021/04/16