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Re: [PATCH v4 3/4] target/xtensa: Make sure that tb->size != 0
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From: |
Max Filippov |
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Subject: |
Re: [PATCH v4 3/4] target/xtensa: Make sure that tb->size != 0 |
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Date: |
Thu, 15 Apr 2021 13:14:39 -0700 |
On Thu, Apr 15, 2021 at 6:03 AM Ilya Leoshkevich <iii@linux.ibm.com> wrote:
>
> tb_gen_code() assumes that tb->size must never be zero, otherwise it
> may produce spurious exceptions. For xtensa this may happen when
> decoding an unknown instruction, when handling a write into the
> CCOUNT or CCOMPARE special register and when single-stepping the first
> instruction of an exception handler.
>
> Fix by pretending that the size of the respective translation block is
> 1 in all these cases.
>
> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
> ---
> target/xtensa/translate.c | 3 +++
> 1 file changed, 3 insertions(+)
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
--
Thanks.
-- Max
- [PATCH v4 0/4] accel/tcg: Make sure that tb->size != 0 after translation, Ilya Leoshkevich, 2021/04/15
- [PATCH v4 1/4] target/s390x: Fix translation exception on illegal instruction, Ilya Leoshkevich, 2021/04/15
- [PATCH v4 3/4] target/xtensa: Make sure that tb->size != 0, Ilya Leoshkevich, 2021/04/15
- Re: [PATCH v4 3/4] target/xtensa: Make sure that tb->size != 0,
Max Filippov <=
- [PATCH v4 4/4] accel/tcg: Assert that tb->size != 0 after translation, Ilya Leoshkevich, 2021/04/15
- [PATCH v4 2/4] target/arm: Make sure that commpage's tb->size != 0, Ilya Leoshkevich, 2021/04/15
- Re: [PATCH v4 0/4] accel/tcg: Make sure that tb->size != 0 after translation, Cornelia Huck, 2021/04/15