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[Bug 1923629] Re: RISC-V Vector Instruction vssub.vv not saturating

From: Frank Chang
Subject: [Bug 1923629] Re: RISC-V Vector Instruction vssub.vv not saturating
Date: Thu, 15 Apr 2021 07:31:04 -0000

This should be a quick fix, we will run couple tests again to ensure the
fix doesn't break anything. Thanks~

** Changed in: qemu
     Assignee: (unassigned) => Frank Chang (frankchang0125)

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  RISC-V Vector Instruction vssub.vv not saturating

Status in QEMU:

Bug description:
  I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an
  incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).

  Here is the bit of the code:

                vmv.v.i         v16, 0
  8f040457      vssub.vv        v8,v16,v8

  I believe the instruction encoding is correct (vssub.vv with vd = v8,
  vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.

  I’ve just tested with what I think is the latest branch (
  https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb
  2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still

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