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[RFC v13 69/80] target/arm: tcg-sve: rename the narrow_vq and change_el
From: |
Claudio Fontana |
Subject: |
[RFC v13 69/80] target/arm: tcg-sve: rename the narrow_vq and change_el functions |
Date: |
Wed, 14 Apr 2021 13:26:39 +0200 |
make them canonical for the module name.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/tcg-sve.h | 6 +++---
linux-user/syscall.c | 2 +-
target/arm/cpu-exceptions-aa64.c | 2 +-
target/arm/tcg/cpregs.c | 2 +-
target/arm/tcg/helper-a64.c | 2 +-
target/arm/tcg/tcg-sve.c | 6 +++---
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h
index 5855bb4289..46e42d1139 100644
--- a/target/arm/tcg/tcg-sve.h
+++ b/target/arm/tcg/tcg-sve.h
@@ -21,9 +21,9 @@ uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map,
bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq,
Error **errp);
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
+void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq);
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
- int new_el, bool el0_a64);
+void tcg_sve_change_el(CPUARMState *env, int old_el,
+ int new_el, bool el0_a64);
#endif /* TCG_SVE_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index d935a98e2f..187fe261d6 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -10932,7 +10932,7 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
vq = MIN(vq, cpu->sve_max_vq);
if (vq < old_vq) {
- aarch64_sve_narrow_vq(env, vq);
+ tcg_sve_narrow_vq(env, vq);
}
env->vfp.zcr_el[1] = vq - 1;
arm_rebuild_hflags(env);
diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-aa64.c
index adaf3bab17..1a3e1d6458 100644
--- a/target/arm/cpu-exceptions-aa64.c
+++ b/target/arm/cpu-exceptions-aa64.c
@@ -119,7 +119,7 @@ void arm_cpu_do_interrupt_aarch64(CPUState *cs)
* Note that new_el can never be 0. If cur_el is 0, then
* el0_a64 is is_a64(), else el0_a64 is ignored.
*/
- aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+ tcg_sve_change_el(env, cur_el, new_el, is_a64(env));
}
if (cur_el < new_el) {
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index 5c5915574e..477d8153a6 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -5814,7 +5814,7 @@ static void zcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
*/
new_len = sve_zcr_len_for_el(env, cur_el);
if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
+ tcg_sve_narrow_vq(env, new_len + 1);
}
}
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 18d4809c23..7bb1a9d7bd 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -1042,7 +1042,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
* Note that cur_el can never be 0. If new_el is 0, then
* el0_a64 is return_to_aa64, else el0_a64 is ignored.
*/
- aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
+ tcg_sve_change_el(env, cur_el, new_el, return_to_aa64);
qemu_mutex_lock_iothread();
arm_call_el_change_hook(env_archcpu(env));
diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c
index 908d2c2f2c..25d5a5867c 100644
--- a/target/arm/tcg/tcg-sve.c
+++ b/target/arm/tcg/tcg-sve.c
@@ -95,7 +95,7 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map,
uint32_t max_vq,
* may well be cheaper than conditionals to restrict the operation
* to the relevant portion of a uint16_t[16].
*/
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
+void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq)
{
int i, j;
uint64_t pmask;
@@ -124,7 +124,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
/*
* Notice a change in SVE vector size when changing EL.
*/
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
+void tcg_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64)
{
ARMCPU *cpu = env_archcpu(env);
@@ -162,6 +162,6 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
/* When changing vector length, clear inaccessible state. */
if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
+ tcg_sve_narrow_vq(env, new_len + 1);
}
}
--
2.26.2
- [RFC v13 55/80] target/arm: create kvm cpu accel class, (continued)
- [RFC v13 55/80] target/arm: create kvm cpu accel class, Claudio Fontana, 2021/04/14
- [RFC v13 60/80] target/arm: cpu-sve: rename functions according to module prefix, Claudio Fontana, 2021/04/14
- [RFC v13 61/80] target/arm: cpu-sve: split TCG and KVM functionality, Claudio Fontana, 2021/04/14
- [RFC v13 54/80] Revert "target/arm: Restrict v8M IDAU to TCG", Claudio Fontana, 2021/04/14
- [RFC v13 56/80] target/arm: move kvm post init initialization to kvm cpu accel, Claudio Fontana, 2021/04/14
- [RFC v13 57/80] target/arm: add tcg cpu accel class, Claudio Fontana, 2021/04/14
- [RFC v13 59/80] target/arm: cpu-sve: new module, Claudio Fontana, 2021/04/14
- [RFC v13 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64, Claudio Fontana, 2021/04/14
- [RFC v13 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool, Claudio Fontana, 2021/04/14
- [RFC v13 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve, Claudio Fontana, 2021/04/14
- [RFC v13 69/80] target/arm: tcg-sve: rename the narrow_vq and change_el functions,
Claudio Fontana <=
- [RFC v13 72/80] target/arm: cpu-common: wrap a64-only check with is_a64, Claudio Fontana, 2021/04/14
- [RFC v13 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features, Claudio Fontana, 2021/04/14
- [RFC v13 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check, Claudio Fontana, 2021/04/14
- [RFC v13 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el, Claudio Fontana, 2021/04/14
- [RFC v13 58/80] target/arm: move TCG gt timer creation code in tcg/, Claudio Fontana, 2021/04/14
- [RFC v13 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64, Claudio Fontana, 2021/04/14
- [RFC v13 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64, Claudio Fontana, 2021/04/14
- [RFC v13 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig, Claudio Fontana, 2021/04/14
- [RFC v13 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules, Claudio Fontana, 2021/04/14
- [RFC v13 76/80] target/arm: cpu64: rename arm_cpu_finalize_features, Claudio Fontana, 2021/04/14