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[RFC v12 58/65] target/arm: tcg-sve: rename the narrow_vq and change_el
From: |
Claudio Fontana |
Subject: |
[RFC v12 58/65] target/arm: tcg-sve: rename the narrow_vq and change_el functions |
Date: |
Fri, 26 Mar 2021 20:36:54 +0100 |
make them canonical for the module name.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/tcg/tcg-sve.h | 4 ++--
linux-user/syscall.c | 2 +-
target/arm/cpu-exceptions-aa64.c | 2 +-
target/arm/tcg/cpregs.c | 2 +-
target/arm/tcg/helper-a64.c | 2 +-
target/arm/tcg/tcg-sve.c | 6 +++---
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h
index 289c1936e1..7ae52fe65e 100644
--- a/target/arm/tcg/tcg-sve.h
+++ b/target/arm/tcg/tcg-sve.h
@@ -23,9 +23,9 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map,
uint32_t max_vq,
/* tcg/helper.c */
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
+void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq);
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
+void tcg_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64);
#endif /* TCG_SVE_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index a271a81d34..e8bd8e1e0f 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -10927,7 +10927,7 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
vq = MIN(vq, cpu->sve_max_vq);
if (vq < old_vq) {
- aarch64_sve_narrow_vq(env, vq);
+ tcg_sve_narrow_vq(env, vq);
}
env->vfp.zcr_el[1] = vq - 1;
arm_rebuild_hflags(env);
diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-aa64.c
index b80f5a99de..13e4c75fd8 100644
--- a/target/arm/cpu-exceptions-aa64.c
+++ b/target/arm/cpu-exceptions-aa64.c
@@ -396,7 +396,7 @@ void arm_cpu_do_interrupt_aarch64(CPUState *cs)
* Note that new_el can never be 0. If cur_el is 0, then
* el0_a64 is is_a64(), else el0_a64 is ignored.
*/
- aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+ tcg_sve_change_el(env, cur_el, new_el, is_a64(env));
}
if (cur_el < new_el) {
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index 0a99490a50..a451e0aaef 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -5815,7 +5815,7 @@ static void zcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
*/
new_len = sve_zcr_len_for_el(env, cur_el);
if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
+ tcg_sve_narrow_vq(env, new_len + 1);
}
}
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 65d7c24578..c1c04b979d 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -1043,7 +1043,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
* Note that cur_el can never be 0. If new_el is 0, then
* el0_a64 is return_to_aa64, else el0_a64 is ignored.
*/
- aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
+ tcg_sve_change_el(env, cur_el, new_el, return_to_aa64);
qemu_mutex_lock_iothread();
arm_call_el_change_hook(env_archcpu(env));
diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c
index 908d2c2f2c..25d5a5867c 100644
--- a/target/arm/tcg/tcg-sve.c
+++ b/target/arm/tcg/tcg-sve.c
@@ -95,7 +95,7 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map,
uint32_t max_vq,
* may well be cheaper than conditionals to restrict the operation
* to the relevant portion of a uint16_t[16].
*/
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
+void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq)
{
int i, j;
uint64_t pmask;
@@ -124,7 +124,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
/*
* Notice a change in SVE vector size when changing EL.
*/
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
+void tcg_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64)
{
ARMCPU *cpu = env_archcpu(env);
@@ -162,6 +162,6 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
/* When changing vector length, clear inaccessible state. */
if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
+ tcg_sve_narrow_vq(env, new_len + 1);
}
}
--
2.26.2
- Re: [RFC v12 53/65] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64, (continued)
- [RFC v12 56/65] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64, Claudio Fontana, 2021/03/26
- [RFC v12 54/65] target/arm: arch_dump: restrict ELFCLASS64 to AArch64, Claudio Fontana, 2021/03/26
- [RFC v12 55/65] target/arm: cpu-exceptions: new module, Claudio Fontana, 2021/03/26
- [RFC v12 57/65] target/arm: tcg-sve: import narrow_vq and change_el functions, Claudio Fontana, 2021/03/26
- [RFC v12 58/65] target/arm: tcg-sve: rename the narrow_vq and change_el functions,
Claudio Fontana <=
- [RFC v12 60/65] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication, Claudio Fontana, 2021/03/26
- [RFC v12 62/65] target/arm: refactor arm_cpu_finalize_features into cpu64, Claudio Fontana, 2021/03/26
- [RFC v12 63/65] XXX target/arm: experiment refactoring cpu "max", Claudio Fontana, 2021/03/26
- [RFC v12 65/65] target/arm: remove v7m stub function for !CONFIG_TCG, Claudio Fontana, 2021/03/26
- [RFC v12 61/65] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el, Claudio Fontana, 2021/03/26