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[RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TC
From: |
Claudio Fontana |
Subject: |
[RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled |
Date: |
Fri, 26 Mar 2021 20:36:12 +0100 |
of note, cpreg lists were previously initialized by TCG first,
and then thrown away and replaced with the data coming from KVM.
Now we just initialize once, either for TCG or for KVM.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 32 ++++++++++++++++++--------------
target/arm/kvm.c | 18 +++++++++---------
target/arm/machine.c | 20 +++++++++++++-------
3 files changed, 40 insertions(+), 30 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 048c904933..e47b09fe18 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -436,9 +436,11 @@ static void arm_cpu_reset(DeviceState *dev)
}
#endif
- hw_breakpoint_update_all(cpu);
- hw_watchpoint_update_all(cpu);
- arm_rebuild_hflags(env);
+ if (tcg_enabled()) {
+ hw_breakpoint_update_all(cpu);
+ hw_watchpoint_update_all(cpu);
+ arm_rebuild_hflags(env);
+ }
}
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
@@ -1319,6 +1321,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
}
+#ifdef CONFIG_TCG
{
uint64_t scale;
@@ -1344,7 +1347,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
arm_gt_hvtimer_cb, cpu);
}
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
@@ -1645,17 +1649,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
unset_feature(env, ARM_FEATURE_PMU);
}
if (arm_feature(env, ARM_FEATURE_PMU)) {
- pmu_init(cpu);
-
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
+ pmu_init(cpu);
arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
- }
#ifndef CONFIG_USER_ONLY
- cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
- cpu);
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
+ cpu);
#endif
+ }
} else {
cpu->isar.id_aa64dfr0 =
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
@@ -1738,10 +1741,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
set_feature(env, ARM_FEATURE_VBAR);
}
- register_cp_regs_for_features(cpu);
- arm_cpu_register_gdb_regs_for_features(cpu);
-
- init_cpreg_list(cpu);
+ if (tcg_enabled()) {
+ register_cp_regs_for_features(cpu);
+ arm_cpu_register_gdb_regs_for_features(cpu);
+ init_cpreg_list(cpu);
+ }
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index d8381ba224..1b093cc52f 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -431,9 +431,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu,
uint64_t regidx)
return &cpu->cpreg_values[res - cpu->cpreg_indexes];
}
-/* Initialize the ARMCPU cpreg list according to the kernel's
- * definition of what CPU registers it knows about (and throw away
- * the previous TCG-created cpreg list).
+/*
+ * Initialize the ARMCPU cpreg list according to the kernel's
+ * definition of what CPU registers it knows about.
+ *
+ * The parallel for TCG is init_cpreg_list() in tcg/
*/
int kvm_arm_init_cpreg_list(ARMCPU *cpu)
{
@@ -475,12 +477,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu)
arraylen++;
}
- cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
- cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
- cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
- arraylen);
- cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
- arraylen);
+ cpu->cpreg_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_values = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
cpu->cpreg_array_len = arraylen;
cpu->cpreg_vmstate_array_len = arraylen;
diff --git a/target/arm/machine.c b/target/arm/machine.c
index e568662cca..2982e8d7f4 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -2,6 +2,7 @@
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "kvm_arm.h"
#include "internals.h"
#include "migration/cpu.h"
@@ -635,7 +636,7 @@ static int cpu_pre_save(void *opaque)
{
ARMCPU *cpu = opaque;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_start(&cpu->env);
}
@@ -670,7 +671,7 @@ static int cpu_post_save(void *opaque)
{
ARMCPU *cpu = opaque;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_finish(&cpu->env);
}
@@ -689,7 +690,7 @@ static int cpu_pre_load(void *opaque)
*/
env->irq_line_state = UINT32_MAX;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_start(&cpu->env);
}
@@ -759,13 +760,13 @@ static int cpu_post_load(void *opaque, int version_id)
}
}
- hw_breakpoint_update_all(cpu);
- hw_watchpoint_update_all(cpu);
+ if (tcg_enabled()) {
+ hw_breakpoint_update_all(cpu);
+ hw_watchpoint_update_all(cpu);
- if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
+ arm_rebuild_hflags(&cpu->env);
}
- arm_rebuild_hflags(&cpu->env);
return 0;
}
@@ -815,8 +816,13 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
VMSTATE_UINT32(env.exception.fsr, ARMCPU),
VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
+#ifdef CONFIG_TCG
VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
+#else
+ VMSTATE_UNUSED(sizeof(QEMUTimer *)),
+ VMSTATE_UNUSED(sizeof(QEMUTimer *)),
+#endif /* CONFIG_TCG */
{
.name = "power_state",
.version_id = 0,
--
2.26.2
- [RFC v12 15/65] target/arm: move cpu definitions to common cpu module, (continued)
- [RFC v12 15/65] target/arm: move cpu definitions to common cpu module, Claudio Fontana, 2021/03/26
- [RFC v12 12/65] target/arm: move physical address translation to cpu-mmu, Claudio Fontana, 2021/03/26
- [RFC v12 17/65] target/arm: tcg: add stubs for some helpers for non-tcg builds, Claudio Fontana, 2021/03/26
- [RFC v12 13/65] target/arm: fix style in preparation of new cpregs module, Claudio Fontana, 2021/03/26
- [RFC v12 18/65] target/arm: move cpsr_read, cpsr_write to cpu_common, Claudio Fontana, 2021/03/26
- [RFC v12 19/65] target/arm: add temporary stub for arm_rebuild_hflags, Claudio Fontana, 2021/03/26
- [RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled,
Claudio Fontana <=
- [RFC v12 20/65] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu, Claudio Fontana, 2021/03/26
- [RFC v12 14/65] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/03/26
- [RFC v12 21/65] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/03/26
- [RFC v12 22/65] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/03/26
- [RFC v12 24/65] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/03/26
- [RFC v12 28/65] target/arm: fixup sve_exception_el code style before move, Claudio Fontana, 2021/03/26