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[RFC v11 29/55] target/arm: cpu: fix style
From: |
Claudio Fontana |
Subject: |
[RFC v11 29/55] target/arm: cpu: fix style |
Date: |
Tue, 23 Mar 2021 16:46:13 +0100 |
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/cpu-sysemu.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 126263dbf4..eb928832a9 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -372,7 +372,8 @@ int sve_exception_el(CPUARMState *env, int el)
if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
bool disabled = false;
- /* The CPACR.ZEN controls traps to EL1:
+ /*
+ * The CPACR.ZEN controls traps to EL1:
* 0, 2 : trap EL0 and EL1 accesses
* 1 : trap only EL0 accesses
* 3 : trap no accesses
@@ -398,7 +399,8 @@ int sve_exception_el(CPUARMState *env, int el)
}
}
- /* CPTR_EL2. Since TZ and TFP are positive,
+ /*
+ * CPTR_EL2. Since TZ and TFP are positive,
* they will be zero when EL2 is not present.
*/
if (el <= 2 && arm_is_el2_enabled(env)) {
@@ -625,10 +627,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
mask = CPSR_I;
- if (env->thumb)
+ if (env->thumb) {
offset = 2;
- else
+ } else {
offset = 4;
+ }
break;
case EXCP_SWI:
new_mode = ARM_CPU_MODE_SVC;
@@ -714,7 +717,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
/* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000;
} else {
- /* ARM v7 architectures provide a vector base address register to remap
+ /*
+ * ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
* This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
@@ -1013,7 +1017,8 @@ void arm_log_exception(int idx)
}
}
-/* Handle a CPU exception for A and R profile CPUs.
+/*
+ * Handle a CPU exception for A and R profile CPUs.
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
--
2.26.2
- Re: [RFC v11 26/55] target/arm: split a15 cpu model and 32bit class functions to cpu32.c, (continued)
- [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/03/23
- Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Alex Bennée, 2021/03/23
- Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/03/24
- Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Alex Bennée, 2021/03/24
- Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Alex Bennée, 2021/03/24
- Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/03/24
- Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Alex Bennée, 2021/03/24
Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Richard Henderson, 2021/03/24
[RFC v11 29/55] target/arm: cpu: fix style,
Claudio Fontana <=
[RFC v11 27/55] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/03/23
[RFC v11 35/55] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM, Claudio Fontana, 2021/03/23
[RFC v11 31/55] target/arm: remove kvm include file for PSCI and arm-powerctl, Claudio Fontana, 2021/03/23
[RFC v11 33/55] target/arm: cleanup cpu includes, Claudio Fontana, 2021/03/23
[RFC v11 32/55] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/03/23