[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR pre
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates |
|
Date: |
Fri, 19 Mar 2021 09:17:37 -0400 |
On Wed, Mar 17, 2021 at 3:44 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 3/17/21 11:39 AM, Alistair Francis wrote:
> > @@ -1312,8 +1320,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
> > target_ulong *ret_value,
> > return -RISCV_EXCP_ILLEGAL_INST;
> > }
> > ret = csr_ops[csrno].predicate(env, csrno);
> > - if (ret < 0) {
> > - return ret;
> > + if (ret > 0) {
> > + return -ret;
> > }
>
> I think you want
>
> if (ret != RISCV_EXCP_NONE) {
> return -ret;
> }
>
> here. But of course this outer interface is still confused until patches 4+5.
> So perhaps it doesn't matter.
It probably doesn't, but it reduces churn so I have fixed this.
Alistair
>
>
> r~
- [PATCH v1 0/5] RISC-V: Convert the CSR access functions to use, Alistair Francis, 2021/03/17
- [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/03/17
- [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates, Alistair Francis, 2021/03/17
- [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/03/17
- [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations, Alistair Francis, 2021/03/17
- [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access, Alistair Francis, 2021/03/17