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[PULL 23/38] tcg/tci: Split out tcg_out_op_rrs
From: |
Richard Henderson |
Subject: |
[PULL 23/38] tcg/tci: Split out tcg_out_op_rrs |
Date: |
Wed, 17 Mar 2021 09:34:29 -0600 |
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 84 +++++++++++++++++++---------------------
1 file changed, 39 insertions(+), 45 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index c5b061fe76..bb4dd76211 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -297,32 +297,38 @@ static void stack_bounds_check(TCGReg base, target_long
offset)
}
}
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
- intptr_t arg2)
+static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
+ TCGReg r0, TCGReg r1, intptr_t i2)
{
uint8_t *old_code_ptr = s->code_ptr;
- stack_bounds_check(arg1, arg2);
- if (type == TCG_TYPE_I32) {
- tcg_out_op_t(s, INDEX_op_ld_i32);
- tcg_out_r(s, ret);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
-#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_ld_i64);
- tcg_out_r(s, ret);
- tcg_out_r(s, arg1);
- tcg_debug_assert(arg2 == (int32_t)arg2);
- tcg_out32(s, arg2);
-#else
- TODO();
-#endif
- }
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tcg_out_r(s, r1);
+ tcg_debug_assert(i2 == (int32_t)i2);
+ tcg_out32(s, i2);
+
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
+ intptr_t offset)
+{
+ stack_bounds_check(base, offset);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset);
+ break;
+#if TCG_TARGET_REG_BITS == 64
+ case TCG_TYPE_I64:
+ tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+}
+
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
uint8_t *old_code_ptr = s->code_ptr;
@@ -444,12 +450,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
CASE_64(st32)
CASE_64(st)
stack_bounds_check(args[1], args[2]);
- tcg_out_op_t(s, opc);
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_debug_assert(args[2] == (int32_t)args[2]);
- tcg_out32(s, args[2]);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_op_rrs(s, opc, args[0], args[1], args[2]);
break;
CASE_32_64(add)
@@ -597,29 +598,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args,
}
}
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
- intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
+ intptr_t offset)
{
- uint8_t *old_code_ptr = s->code_ptr;
-
- stack_bounds_check(arg1, arg2);
- if (type == TCG_TYPE_I32) {
- tcg_out_op_t(s, INDEX_op_st_i32);
- tcg_out_r(s, arg);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
+ stack_bounds_check(base, offset);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset);
+ break;
#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_st_i64);
- tcg_out_r(s, arg);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
-#else
- TODO();
+ case TCG_TYPE_I64:
+ tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset);
+ break;
#endif
+ default:
+ g_assert_not_reached();
}
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
--
2.25.1
- [PULL 21/38] tcg/tci: Implement the disassembler properly, (continued)
- [PULL 21/38] tcg/tci: Implement the disassembler properly, Richard Henderson, 2021/03/17
- [PULL 27/38] tcg/tci: Split out tcg_out_op_rrr, Richard Henderson, 2021/03/17
- [PULL 30/38] tcg/tci: Split out tcg_out_op_rrrbb, Richard Henderson, 2021/03/17
- [PULL 28/38] tcg/tci: Split out tcg_out_op_rrrc, Richard Henderson, 2021/03/17
- [PULL 24/38] tcg/tci: Split out tcg_out_op_l, Richard Henderson, 2021/03/17
- [PULL 25/38] tcg/tci: Split out tcg_out_op_p, Richard Henderson, 2021/03/17
- [PULL 36/38] tcg/tci: Split out tcg_out_op_v, Richard Henderson, 2021/03/17
- [PULL 17/38] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits, Richard Henderson, 2021/03/17
- [PULL 15/38] tcg/tci: Split out tci_args_rrrr, Richard Henderson, 2021/03/17
- [PULL 16/38] tcg/tci: Clean up deposit operations, Richard Henderson, 2021/03/17
- [PULL 23/38] tcg/tci: Split out tcg_out_op_rrs,
Richard Henderson <=
- [PULL 22/38] tcg/tci: Push opcode emit into each case, Richard Henderson, 2021/03/17
- [PULL 31/38] tcg/tci: Split out tcg_out_op_rrcl, Richard Henderson, 2021/03/17
- [PULL 33/38] tcg/tci: Split out tcg_out_op_rrrr, Richard Henderson, 2021/03/17
- [PULL 35/38] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}, Richard Henderson, 2021/03/17
- [PULL 32/38] tcg/tci: Split out tcg_out_op_rrrrrr, Richard Henderson, 2021/03/17
- [PULL 38/38] tcg: Fix prototypes for tcg_out_vec_op and tcg_out_op, Richard Henderson, 2021/03/17
- [PULL 37/38] tcg/tci: Split out tcg_out_op_r[iI], Richard Henderson, 2021/03/17
- [PULL 34/38] tcg/tci: Split out tcg_out_op_rrrrcl, Richard Henderson, 2021/03/17
- [PULL 29/38] tcg/tci: Split out tcg_out_op_rrrrrc, Richard Henderson, 2021/03/17
- Re: [PULL 00/38] tcg patch queue for 6.0, Peter Maydell, 2021/03/18