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[PATCH 3/5] tcg: Elide memory barriers implied by the host memory model
From: |
Richard Henderson |
Subject: |
[PATCH 3/5] tcg: Elide memory barriers implied by the host memory model |
Date: |
Tue, 16 Mar 2021 16:07:33 -0600 |
Reduce the set of required barriers to those needed by
the host right from the beginning.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 76dc7d8dc5..c8501508c2 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -102,8 +102,13 @@ void tcg_gen_mb(TCGBar mb_type)
* (i.e. !(tb_cflags & CF_PARALLEL)), however, even with a single cpu
* we have i/o threads running in parallel, and lack of memory order
* can result in e.g. virtio queue entries being read incorrectly.
+ *
+ * That said, we can elide anything which the host provides for free.
*/
- tcg_gen_op1(INDEX_op_mb, mb_type);
+ mb_type &= ~TCG_TARGET_DEFAULT_MO;
+ if (mb_type & TCG_MO_ALL) {
+ tcg_gen_op1(INDEX_op_mb, mb_type);
+ }
}
/* 32 bit ops */
--
2.25.1
- [PATCH 0/5] tcg: Issue memory barriers for guest memory model, Richard Henderson, 2021/03/16
- [PATCH 1/5] tcg: Decode the operand to INDEX_op_mb in dumps, Richard Henderson, 2021/03/16
- [PATCH 2/5] tcg: Do not elide memory barriers for CF_PARALLEL, Richard Henderson, 2021/03/16
- [PATCH 3/5] tcg: Elide memory barriers implied by the host memory model,
Richard Henderson <=
- [PATCH 5/5] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2021/03/16
- [PATCH 4/5] tcg: Create tcg_req_mo, Richard Henderson, 2021/03/16
- Re: [PATCH 0/5] tcg: Issue memory barriers for guest memory model, no-reply, 2021/03/16