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[PULL 5/7] tricore: fixed faulty conditions for extr and imask
From: |
Bastian Koppelmann |
Subject: |
[PULL 5/7] tricore: fixed faulty conditions for extr and imask |
Date: |
Sun, 14 Mar 2021 14:55:11 +0100 |
From: Andreas Konopik <andreas.konopik@efs-auto.de>
According to the TC 1.3.1. Architecture Manual [1; page 174], results are
undefined, if pos + width > 32 and not 31 or if width = 0.
We found this error because of a different behavior between qemu-tricore
and the real tricore processor. For pos + width = 32, qemu-tricore did not
generate any intermediate code and ran into a different state compared to
the real hardware.
[1]
https://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352
[BK: Add the why to the commit message]
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Message-Id: <20210211115329.8984-2-david.brenken@efs-auto.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7752630ac1..ebeddf8f4a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5777,8 +5777,8 @@ static void decode_rcpw_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RCPW_IMASK:
CHECK_REG_PAIR(r2);
- /* if pos + width > 31 undefined result */
- if (pos + width <= 31) {
+ /* if pos + width > 32 undefined result */
+ if (pos + width <= 32) {
tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
}
@@ -6999,7 +6999,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RRPW_EXTR:
- if (pos + width <= 31) {
+ if (pos + width <= 32) {
/* optimize special cases */
if ((pos == 0) && (width == 8)) {
tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
@@ -7021,7 +7021,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
break;
case OPC2_32_RRPW_IMASK:
CHECK_REG_PAIR(r3);
- if (pos + width <= 31) {
+ if (pos + width <= 32) {
tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
}
--
2.30.1
- [PULL 0/7] tricore queue, Bastian Koppelmann, 2021/03/14
- [PULL 2/7] target/tricore: Replace magic value by MMU_DATA_LOAD definition, Bastian Koppelmann, 2021/03/14
- [PULL 1/7] tricore: added triboard with tc27x_soc, Bastian Koppelmann, 2021/03/14
- [PULL 3/7] target/tricore: Pass MMUAccessType to get_physical_address(), Bastian Koppelmann, 2021/03/14
- [PULL 4/7] target/tricore: Remove unused definitions, Bastian Koppelmann, 2021/03/14
- [PULL 5/7] tricore: fixed faulty conditions for extr and imask,
Bastian Koppelmann <=
- [PULL 6/7] target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2, Bastian Koppelmann, 2021/03/14
- [PULL 7/7] target/tricore: Fix OPC2_32_RRPW_EXTR for width=0, Bastian Koppelmann, 2021/03/14
- Re: [PULL 0/7] tricore queue, Peter Maydell, 2021/03/15