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[PULL 15/39] target/arm: Update CNTP for PREDDESC
From: |
Peter Maydell |
Subject: |
[PULL 15/39] target/arm: Update CNTP for PREDDESC |
Date: |
Fri, 12 Mar 2021 13:51:16 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sve_helper.c | 6 +++---
target/arm/translate-sve.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 8e0a5d30a53..a95bbece4f3 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2836,12 +2836,12 @@ uint32_t HELPER(sve_brkns)(void *vd, void *vn, void
*vg, uint32_t pred_desc)
uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
{
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
- intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
+ intptr_t words = DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ), 8);
+ intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
uint64_t *n = vn, *g = vg, sum = 0, mask = pred_esz_masks[esz];
intptr_t i;
- for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) {
+ for (i = 0; i < words; ++i) {
uint64_t t = n[i] & g[i] & mask;
sum += ctpop64(t);
}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index c0212e6b08a..722805cf99e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2967,11 +2967,11 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int
esz, int pn, int pg)
} else {
TCGv_ptr t_pn = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr();
- unsigned desc;
+ unsigned desc = 0;
TCGv_i32 t_desc;
- desc = psz - 2;
- desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz);
+ desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
+ desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
--
2.20.1
- [PULL 00/39] target-arm queue, Peter Maydell, 2021/03/12
- [PULL 01/39] hw/misc: versal: Add a model of the XRAM controller, Peter Maydell, 2021/03/12
- [PULL 02/39] hw/arm: versal: Add support for the XRAMs, Peter Maydell, 2021/03/12
- [PULL 06/39] hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set, Peter Maydell, 2021/03/12
- [PULL 03/39] intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate, Peter Maydell, 2021/03/12
- [PULL 05/39] virtio-iommu: Handle non power of 2 range invalidations, Peter Maydell, 2021/03/12
- [PULL 07/39] hw/arm/smmuv3: Enforce invalidation on a power of two range, Peter Maydell, 2021/03/12
- [PULL 04/39] dma: Introduce dma_aligned_pow2_mask(), Peter Maydell, 2021/03/12
- [PULL 13/39] target/arm: Update find_last_active for PREDDESC, Peter Maydell, 2021/03/12
- [PULL 15/39] target/arm: Update CNTP for PREDDESC,
Peter Maydell <=
- [PULL 08/39] hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling, Peter Maydell, 2021/03/12
- [PULL 09/39] hw/arm/smmuv3: Uniformize sid traces, Peter Maydell, 2021/03/12
- [PULL 11/39] target/arm: Fix sve_zip_p vs odd vector lengths, Peter Maydell, 2021/03/12
- [PULL 21/39] tests/acceptance: update sunxi kernel from armbian to 5.10.16, Peter Maydell, 2021/03/12
- [PULL 14/39] target/arm: Update BRKA, BRKB, BRKN for PREDDESC, Peter Maydell, 2021/03/12
- [PULL 18/39] hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value, Peter Maydell, 2021/03/12
- [PULL 24/39] accel: kvm: Fix kvm_type invocation, Peter Maydell, 2021/03/12
- [PULL 27/39] hw/misc: Add NPCM7XX MFT Module, Peter Maydell, 2021/03/12
- [PULL 29/39] hw/arm: Connect PWM fans in NPCM7XX boards, Peter Maydell, 2021/03/12
- [PULL 35/39] hw/display/pxa2xx_lcd: Remove dest_width state field, Peter Maydell, 2021/03/12