Re: [PATCH 1/3] Andes RISC-V PLIC

[Dylan Jhong]

On Wed, Mar 10, 2021 at 02:05:51PM +0800, Bin Meng wrote:
> On Wed, Mar 10, 2021 at 11:34 AM Dylan Jhong <dylan@andestech.com> wrote:
> >
> > Andes PLIC (Platform-Level Interrupt Controller) device provides an
> > interrupt controller functionality based on Andes's PLIC specification.
> >
> > The Andes PLIC can handle either external interrupts (PLIC)
> > or interprocessor interrupts (PLICSW).
> >
> > While Andes PLIC spec includes vector interrupt and interrupt preemption,
> > we leave them as future items for now.
> >
> > Signed-off-by: Dylan Jhong <dylan@andestech.com>
> > Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> > ---
> >  hw/intc/Kconfig              |   3 +
> >  hw/intc/andes_plic.c         | 505 +++++++++++++++++++++++++++++++++++
> >  hw/intc/meson.build          |   1 +
> >  include/hw/intc/andes_plic.h | 130 +++++++++
> >  4 files changed, 639 insertions(+)
> >  create mode 100644 hw/intc/andes_plic.c
> >  create mode 100644 include/hw/intc/andes_plic.h
> 
> Is the Andes PLIC spec public available?
>

Please refer to Andes website
http://www.andestech.com/en/products-solutions/product-documentation/

> What's the difference between Andres's implementation and the SiFive's?
> 

Currently, the Andes's PLIC specification allows the following functions:

Preemptive Priority Interrupt, Vectored Mode Interrupt Dispatching and
Software-Generated Interrupt.

In this patch, we only implement "Software-Generated Interrupt" feature.
For the other PLIC features, we'll leave them as future items for now.

> Regards,
> Bin