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[PULL 02/45] target/arm: Fix SCR RES1 handling
From: |
Peter Maydell |
Subject: |
[PULL 02/45] target/arm: Fix SCR RES1 handling |
Date: |
Thu, 11 Feb 2021 12:58:17 +0000 |
From: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
to 1 only when there is no support for AArch32 at EL1 or above.
The reset value will be 0x30 only if the CPU is AArch64-only; if there
is support for AArch32 at EL1 or above, it will be reset to 0.
Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
is supported at EL1 or above.
Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
target/arm/helper.c | 16 ++++++++++++++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d080239863c..39633f73f36 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4033,6 +4033,11 @@ static inline bool isar_feature_aa64_aa32(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
}
+static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
+}
+
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1a64bd748ce..51330a0c489 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2024,7 +2024,10 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
ARMCPU *cpu = env_archcpu(env);
if (ri->state == ARM_CP_STATE_AA64) {
- value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
+ if (arm_feature(env, ARM_FEATURE_AARCH64) &&
+ !cpu_isar_feature(aa64_aa32_el1, cpu)) {
+ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
+ }
valid_mask &= ~SCR_NET;
if (cpu_isar_feature(aa64_lor, cpu)) {
@@ -2063,6 +2066,15 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
raw_write(env, ri, value);
}
+static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ /*
+ * scr_write will set the RES1 bits on an AArch64-only CPU.
+ * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
+ */
+ scr_write(env, ri, 0);
+}
+
static CPAccessResult access_aa64_tid2(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
@@ -5785,7 +5797,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
- .resetvalue = 0, .writefn = scr_write },
+ .resetfn = scr_reset, .writefn = scr_write },
{ .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
--
2.20.1
- [PULL 00/45] target-arm queue, Peter Maydell, 2021/02/11
- [PULL 01/45] target/arm: Don't migrate CPUARMState.features, Peter Maydell, 2021/02/11
- [PULL 05/45] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate, Peter Maydell, 2021/02/11
- [PULL 07/45] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU, Peter Maydell, 2021/02/11
- [PULL 04/45] target/arm: Add support for FEAT_DIT, Data Independent Timing, Peter Maydell, 2021/02/11
- [PULL 02/45] target/arm: Fix SCR RES1 handling,
Peter Maydell <=
- [PULL 08/45] arm: Update infocenter.arm.com URLs, Peter Maydell, 2021/02/11
- [PULL 03/45] hw/arm: Remove GPIO from unimplemented NPCM7XX, Peter Maydell, 2021/02/11
- [PULL 06/45] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU, Peter Maydell, 2021/02/11
- [PULL 09/45] accel/tcg: Add URL of clang bug to comment about our workaround, Peter Maydell, 2021/02/11
- [PULL 10/45] tcg: Introduce target-specific page data for user-only, Peter Maydell, 2021/02/11
- [PULL 11/45] linux-user: Introduce PAGE_ANON, Peter Maydell, 2021/02/11
- [PULL 12/45] exec: Use uintptr_t for guest_base, Peter Maydell, 2021/02/11
- [PULL 13/45] exec: Use uintptr_t in cpu_ldst.h, Peter Maydell, 2021/02/11
- [PULL 16/45] linux-user: Tidy VERIFY_READ/VERIFY_WRITE, Peter Maydell, 2021/02/11