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[PULL 25/33] target/arm: Update ZIP, UZP, TRN for pred_desc
From: |
Peter Maydell |
Subject: |
[PULL 25/33] target/arm: Update ZIP, UZP, TRN for pred_desc |
Date: |
Tue, 19 Jan 2021 15:10:56 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Update all users of do_perm_pred3 for the new
predicate descriptor field definitions.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210113062650.593824-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sve_helper.c | 18 +++++++++---------
target/arm/translate-sve.c | 12 ++++--------
2 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index ff01851bf28..7eec4b6b73a 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1868,9 +1868,9 @@ static uint64_t compress_bits(uint64_t x, int n)
void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
{
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
- int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
- intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
+ int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
+ intptr_t high = FIELD_EX32(pred_desc, PREDDESC, DATA);
uint64_t *d = vd;
intptr_t i;
@@ -1929,9 +1929,9 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
{
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
- int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
- int odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1) << esz;
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
+ int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
+ int odd = FIELD_EX32(pred_desc, PREDDESC, DATA) << esz;
uint64_t *d = vd, *n = vn, *m = vm;
uint64_t l, h;
intptr_t i;
@@ -1986,9 +1986,9 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
void HELPER(sve_trn_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
{
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
- uintptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
- bool odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
+ int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
+ int odd = FIELD_EX32(pred_desc, PREDDESC, DATA);
uint64_t *d = vd, *n = vn, *m = vm;
uint64_t mask;
int shr, shl;
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index efcb646f729..0baca176a09 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2110,19 +2110,15 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz
*a, bool high_odd,
unsigned vsz = pred_full_reg_size(s);
- /* Predicate sizes may be smaller and cannot use simd_desc.
- We cannot round up, as we do elsewhere, because we need
- the exact size for ZIP2 and REV. We retain the style for
- the other helpers for consistency. */
TCGv_ptr t_d = tcg_temp_new_ptr();
TCGv_ptr t_n = tcg_temp_new_ptr();
TCGv_ptr t_m = tcg_temp_new_ptr();
TCGv_i32 t_desc;
- int desc;
+ uint32_t desc = 0;
- desc = vsz - 2;
- desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz);
- desc = deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd);
+ desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
+ desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
+ desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
--
2.20.1
- [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table, (continued)
- [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table, Peter Maydell, 2021/01/19
- [PULL 15/33] target/arm: translate NS bit in page-walks, Peter Maydell, 2021/01/19
- [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers, Peter Maydell, 2021/01/19
- [PULL 17/33] target/arm: secure stage 2 translation regime, Peter Maydell, 2021/01/19
- [PULL 21/33] target/arm: enable Secure EL2 in max CPU, Peter Maydell, 2021/01/19
- [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup, Peter Maydell, 2021/01/19
- [PULL 16/33] target/arm: generalize 2-stage page-walk condition, Peter Maydell, 2021/01/19
- [PULL 18/33] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, Peter Maydell, 2021/01/19
- [PULL 22/33] target/arm: refactor vae1_tlbmask(), Peter Maydell, 2021/01/19
- [PULL 24/33] target/arm: Update PFIRST, PNEXT for pred_desc, Peter Maydell, 2021/01/19
- [PULL 25/33] target/arm: Update ZIP, UZP, TRN for pred_desc,
Peter Maydell <=
- [PULL 23/33] target/arm: Introduce PREDDESC field definitions, Peter Maydell, 2021/01/19
- [PULL 20/33] target/arm: Implement SCR_EL2.EEL2, Peter Maydell, 2021/01/19
- [PULL 19/33] target/arm: revector to run-time pick target EL, Peter Maydell, 2021/01/19
- [PULL 27/33] hw/misc/pvpanic: split-out generic and bus dependent code, Peter Maydell, 2021/01/19
- [PULL 28/33] hw/misc/pvpanic: add PCI interface support, Peter Maydell, 2021/01/19
- [PULL 26/33] target/arm: Update REV, PUNPK for pred_desc, Peter Maydell, 2021/01/19
- [PULL 29/33] pvpanic : update pvpanic spec document, Peter Maydell, 2021/01/19
- [PULL 33/33] docs: Build and install all the docs in a single manual, Peter Maydell, 2021/01/19
- [PULL 32/33] target/arm/m_helper: Silence GCC 10 maybe-uninitialized error, Peter Maydell, 2021/01/19
- [PULL 31/33] npcm7xx_adc-test: Fix memleak in adc_qom_set, Peter Maydell, 2021/01/19