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Re: [PATCH v2 02/12] hw/block/nvme: fix 64 bit register hi/lo split writ
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From: |
Minwoo Im |
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Subject: |
Re: [PATCH v2 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes |
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Date: |
Tue, 19 Jan 2021 11:09:31 +0900 |
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User-agent: |
Mutt/1.11.4 (2019-03-13) |
On 21-01-18 20:53:24, Klaus Jensen wrote:
> On Jan 18 21:59, Minwoo Im wrote:
> > > The spec requires aligned 32 bit accesses (or the size of the register),
> > > so maybe it's about time we actually ignore instead of falling through.
> >
> > Agreed.
> >
>
> On the other hand.
>
> The spec just allows undefined behavior if the alignment or size
> requirement is violated. So falling through is not wrong.
If so, maybe we just can make this MMIO region support under 4bytes
access with error messaging. I don't think we should not support them
on purpose because spec says it just results in undefined behaviors
which is just undefined how to handle them.
[PATCH v2 03/12] hw/block/nvme: indicate CMB support through controller capabilities register, Klaus Jensen, 2021/01/18
[PATCH v2 04/12] hw/block/nvme: move msix table and pba to BAR 0, Klaus Jensen, 2021/01/18
[PATCH v2 05/12] hw/block/nvme: allow cmb and pmr to coexist, Klaus Jensen, 2021/01/18
[PATCH v2 06/12] hw/block/nvme: rename PMR/CMB shift/mask fields, Klaus Jensen, 2021/01/18
[PATCH v2 07/12] hw/block/nvme: remove redundant zeroing of PMR registers, Klaus Jensen, 2021/01/18