[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PULL 00/12] riscv-to-apply queue
|
From: |
Peter Maydell |
|
Subject: |
Re: [PULL 00/12] riscv-to-apply queue |
|
Date: |
Mon, 18 Jan 2021 12:03:39 +0000 |
On Sun, 17 Jan 2021 at 21:54, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15
> 22:21:21 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3
>
> for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e:
>
> riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800)
>
> ----------------------------------------------------------------
> First RISC-V PR for 6.0
>
> This PR:
> - Fixes some issues with the m25p80
> - Improves GDB support for RISC-V
> - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
> - Enforces PMP exceptions correctly
> - Fixes some Coverity issues
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
- [PULL 12/12] riscv: Pass RISCVHartArrayState by pointer, (continued)
- [PULL 12/12] riscv: Pass RISCVHartArrayState by pointer, Alistair Francis, 2021/01/17
- [PULL 03/12] gdb: riscv: Add target description, Alistair Francis, 2021/01/17
- [PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type, Alistair Francis, 2021/01/17
- [PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured, Alistair Francis, 2021/01/17
- [PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB, Alistair Francis, 2021/01/17
- [PULL 09/12] target/riscv: Add CSR name in the CSR function table, Alistair Francis, 2021/01/17
- [PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite, Alistair Francis, 2021/01/17
- [PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically, Alistair Francis, 2021/01/17
- [PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external, Alistair Francis, 2021/01/17
- [PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs, Alistair Francis, 2021/01/17
- Re: [PULL 00/12] riscv-to-apply queue,
Peter Maydell <=