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[PATCH 16/19] target/arm: revector to run-time pick target EL
From: |
remi . denis . courmont |
Subject: |
[PATCH 16/19] target/arm: revector to run-time pick target EL |
Date: |
Tue, 12 Jan 2021 12:45:08 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to
the upper (64-bit) EL. With Secure EL2 support, we can no longer assume
that that is always EL3, so make room for the value to be computed at
run-time.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
target/arm/translate.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f5acd32e76..8b6b7355c9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1094,6 +1094,22 @@ static void unallocated_encoding(DisasContext *s)
default_exception_el(s));
}
+static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
+ TCGv_i32 tcg_el)
+{
+ TCGv_i32 tcg_excp;
+ TCGv_i32 tcg_syn;
+
+ gen_set_condexec(s);
+ gen_set_pc_im(s, s->pc_curr);
+ tcg_excp = tcg_const_i32(excp);
+ tcg_syn = tcg_const_i32(syn);
+ gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el);
+ tcg_temp_free_i32(tcg_syn);
+ tcg_temp_free_i32(tcg_excp);
+ s->base.is_jmp = DISAS_NORETURN;
+}
+
/* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s)
{
@@ -2818,8 +2834,11 @@ static bool msr_banked_access_decode(DisasContext *s,
int r, int sysm, int rn,
/* If we're in Secure EL1 (which implies that EL3 is AArch64)
* then accesses to Mon registers trap to EL3
*/
- exc_target = 3;
- goto undef;
+ TCGv_i32 tcg_el = tcg_const_i32(3);
+
+ gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
+ tcg_temp_free_i32(tcg_el);
+ return false;
}
break;
case ARM_CPU_MODE_HYP:
--
2.30.0
- [PATCH 11/19] target/arm: do S1_ptw_translate() before address space lookup, (continued)
- [PATCH 11/19] target/arm: do S1_ptw_translate() before address space lookup, remi . denis . courmont, 2021/01/12
- [PATCH 14/19] target/arm: secure stage 2 translation regime, remi . denis . courmont, 2021/01/12
- [PATCH 12/19] target/arm: translate NS bit in page-walks, remi . denis . courmont, 2021/01/12
- [PATCH 07/19] target/arm: add 64-bit S-EL2 to EL exception table, remi . denis . courmont, 2021/01/12
- [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension, remi . denis . courmont, 2021/01/12
- [PATCH 13/19] target/arm: generalize 2-stage page-walk condition, remi . denis . courmont, 2021/01/12
- [PATCH 16/19] target/arm: revector to run-time pick target EL,
remi . denis . courmont <=
- [PATCH 18/19] target/arm: enable Secure EL2 in max CPU, remi . denis . courmont, 2021/01/12
- [PATCH 19/19] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2021/01/12
- [PATCH 15/19] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2021/01/12
- Re: [PATCHv5 00/19] ARMv8.4-A Secure EL2, Peter Maydell, 2021/01/19