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Re: [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table
From: |
Peter Maydell |
Subject: |
Re: [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table |
Date: |
Tue, 12 Jan 2021 09:55:54 +0000 |
On Tue, 12 Jan 2021 at 00:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote:
> > From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> >
> > With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in
> > secure mode, though it can only be AArch64.
> >
> > This patch adds the target EL for exceptions from 64-bit S-EL2.
> >
> > It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure
> > mode. Those values were never used in practice as the effective value of
> > HCR was always 0 in secure mode.
> >
> > Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> > ---
> > target/arm/helper.c | 10 +++++-----
> > target/arm/op_helper.c | 4 ++--
> > 2 files changed, 7 insertions(+), 7 deletions(-)
>
> At some point I think it would be worthwhile to convert that target_el_table
> back to code. It is really hard to follow with 6 indicies. Not your fault.
I think that there's value in having it be expressed as data
rather than code because then it can be compared with the equivalent
tables in the Arm ARM. I agree that a 6-index array is getting
a bit unreadable, but maybe there's a more readable data format
we could find ?
-- PMM