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[PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field
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From: |
frank . chang |
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Subject: |
[PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field |
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Date: |
Tue, 12 Jan 2021 17:38:39 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a70a78386da..c8b1e4954ec 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -579,7 +579,7 @@ static int write_misa(CPURISCVState *env, int csrno,
target_ulong val)
val &= env->misa_mask;
/* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
--
2.17.1
- [PATCH v6 00/72] support vector extension v1.0, frank . chang, 2021/01/12
- [PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/01/12
- [PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/01/12
- [PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/01/12
- [PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/01/12
- [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field,
frank . chang <=
- [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/01/12
- [PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/01/12
- [PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/01/12
- [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/01/12
- [PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/01/12