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[PATCH v6 19/23] tcg: Add tcg_reg_alloc_dup2
From: |
Richard Henderson |
Subject: |
[PATCH v6 19/23] tcg: Add tcg_reg_alloc_dup2 |
Date: |
Mon, 11 Jan 2021 07:19:42 -1000 |
There are several ways we can expand a vector dup of a 64-bit
element on a 32-bit host.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5b0e42be91..8f8badb61c 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -4084,6 +4084,98 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
}
}
+static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op)
+{
+ const TCGLifeData arg_life = op->life;
+ TCGTemp *ots, *itsl, *itsh;
+ TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64;
+
+ /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
+ tcg_debug_assert(TCGOP_VECE(op) == MO_64);
+
+ ots = arg_temp(op->args[0]);
+ itsl = arg_temp(op->args[1]);
+ itsh = arg_temp(op->args[2]);
+
+ /* ENV should not be modified. */
+ tcg_debug_assert(!temp_readonly(ots));
+
+ /* Allocate the output register now. */
+ if (ots->val_type != TEMP_VAL_REG) {
+ TCGRegSet allocated_regs = s->reserved_regs;
+ TCGRegSet dup_out_regs =
+ tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
+
+ /* Make sure to not spill the input registers. */
+ if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) {
+ tcg_regset_set_reg(allocated_regs, itsl->reg);
+ }
+ if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) {
+ tcg_regset_set_reg(allocated_regs, itsh->reg);
+ }
+
+ ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs,
+ op->output_pref[0], ots->indirect_base);
+ ots->val_type = TEMP_VAL_REG;
+ ots->mem_coherent = 0;
+ s->reg_to_temp[ots->reg] = ots;
+ }
+
+ /* Promote dup2 of immediates to dupi_vec. */
+ if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) {
+ uint64_t val = deposit64(itsl->val, 32, 32, itsh->val);
+ MemOp vece = MO_64;
+
+ if (val == dup_const(MO_8, val)) {
+ vece = MO_8;
+ } else if (val == dup_const(MO_16, val)) {
+ vece = MO_16;
+ } else if (val == dup_const(MO_32, val)) {
+ vece = MO_32;
+ }
+
+ tcg_out_dupi_vec(s, vtype, vece, ots->reg, val);
+ goto done;
+ }
+
+ /* If the two inputs form one 64-bit value, try dupm_vec. */
+ if (itsl + 1 == itsh && itsl->base_type == TCG_TYPE_I64) {
+ if (!itsl->mem_coherent) {
+ temp_sync(s, itsl, s->reserved_regs, 0, 0);
+ }
+ if (!itsh->mem_coherent) {
+ temp_sync(s, itsh, s->reserved_regs, 0, 0);
+ }
+#ifdef HOST_WORDS_BIGENDIAN
+ TCGTemp *its = itsh;
+#else
+ TCGTemp *its = itsl;
+#endif
+ if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg,
+ its->mem_base->reg, its->mem_offset)) {
+ goto done;
+ }
+ }
+
+ /* Fall back to generic expansion. */
+ return false;
+
+ done:
+ if (IS_DEAD_ARG(1)) {
+ temp_dead(s, itsl);
+ }
+ if (IS_DEAD_ARG(2)) {
+ temp_dead(s, itsh);
+ }
+ if (NEED_SYNC_ARG(0)) {
+ temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0));
+ } else if (IS_DEAD_ARG(0)) {
+ temp_dead(s, ots);
+ }
+ return true;
+}
+
#ifdef TCG_TARGET_STACK_GROWSUP
#define STACK_DIR(x) (-(x))
#else
@@ -4501,6 +4593,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
case INDEX_op_call:
tcg_reg_alloc_call(s, op);
break;
+ case INDEX_op_dup2_vec:
+ if (tcg_reg_alloc_dup2(s, op)) {
+ break;
+ }
+ /* fall through */
default:
/* Sanity check that we've not introduced any unhandled opcodes. */
tcg_debug_assert(tcg_op_supported(opc));
--
2.25.1
- [PATCH v6 02/23] tcg: Increase tcg_out_dupi_vec immediate to int64_t, (continued)
- [PATCH v6 02/23] tcg: Increase tcg_out_dupi_vec immediate to int64_t, Richard Henderson, 2021/01/11
- [PATCH v6 06/23] tcg: Rename struct tcg_temp_info to TempOptInfo, Richard Henderson, 2021/01/11
- [PATCH v6 05/23] tcg: Expand TCGTemp.val to 64-bits, Richard Henderson, 2021/01/11
- [PATCH v6 04/23] tcg: Add temp_readonly, Richard Henderson, 2021/01/11
- [PATCH v6 08/23] tcg: Introduce TYPE_CONST temporaries, Richard Henderson, 2021/01/11
- [PATCH v6 03/23] tcg: Consolidate 3 bits into enum TCGTempKind, Richard Henderson, 2021/01/11
- [PATCH v6 09/23] tcg/optimize: Improve find_better_copy, Richard Henderson, 2021/01/11
- [PATCH v6 12/23] tcg: Convert tcg_gen_dupi_vec to TCG_CONST, Richard Henderson, 2021/01/11
- [PATCH v6 15/23] tcg: Use tcg_constant_{i32,i64} with tcg plugins, Richard Henderson, 2021/01/11
- [PATCH v6 16/23] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders, Richard Henderson, 2021/01/11
- [PATCH v6 19/23] tcg: Add tcg_reg_alloc_dup2,
Richard Henderson <=
- [PATCH v6 21/23] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec, Richard Henderson, 2021/01/11
- [PATCH v6 17/23] tcg/tci: Add special tci_movi_{i32,i64} opcodes, Richard Henderson, 2021/01/11
- [PATCH v6 23/23] tcg/aarch64: Use tcg_constant_vec with tcg vec expanders, Richard Henderson, 2021/01/11
- [PATCH v6 20/23] tcg/i386: Use tcg_constant_vec with tcg vec expanders, Richard Henderson, 2021/01/11
- [PATCH v6 22/23] tcg/ppc: Use tcg_constant_vec with tcg vec expanders, Richard Henderson, 2021/01/11
- [PATCH v6 10/23] tcg/optimize: Adjust TempOptInfo allocation, Richard Henderson, 2021/01/11
- [PATCH v6 07/23] tcg: Expand TempOptInfo to 64-bits, Richard Henderson, 2021/01/11
- [PATCH v6 11/23] tcg/optimize: Use tcg_constant_internal with constant folding, Richard Henderson, 2021/01/11
- [PATCH v6 14/23] tcg: Use tcg_constant_{i32, i64} with tcg int expanders, Richard Henderson, 2021/01/11
- [PATCH v6 18/23] tcg: Remove movi and dupi opcodes, Richard Henderson, 2021/01/11
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