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[PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set |
Date: |
Thu, 7 Jan 2021 23:22:21 +0100 |
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-20-f4bug@amsat.org>
---
target/mips/meson.build | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5a49951c6d7..596eb1aeeb3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,9 +1,11 @@
mips_ss = ss.source_set()
mips_ss.add(files(
'cpu.c',
+ 'gdbstub.c',
+))
+mips_ss.add(when: 'CONFIG_TCG', if_true: files(
'dsp_helper.c',
'fpu_helper.c',
- 'gdbstub.c',
'lmmi_helper.c',
'msa_helper.c',
'op_helper.c',
@@ -15,11 +17,13 @@
mips_softmmu_ss = ss.source_set()
mips_softmmu_ss.add(files(
'addr.c',
- 'cp0_helper.c',
'cp0_timer.c',
'machine.c',
'mips-semi.c',
))
+mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
+ 'cp0_helper.c',
+))
target_arch += {'mips': mips_ss}
target_softmmu_arch += {'mips': mips_softmmu_ss}
--
2.26.2
- [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c, (continued)
- [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 25/66] target/mips: Fix code style for checkpatch.pl, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 28/66] target/mips/translate: Extract DisasContext structure, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 29/66] target/mips/translate: Add declarations for generic code, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 31/66] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h', Philippe Mathieu-Daudé, 2021/01/07
- [PULL 33/66] target/mips: Extract FPU specific definitions to translate.h, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set,
Philippe Mathieu-Daudé <=
- [PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 37/66] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 38/66] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 40/66] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 41/66] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2021/01/07