Re: [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode

[Jiaxun Yang]

在 2021/1/7 上午2:37, Philippe Mathieu-Daudé 写道:
> On Wed, Jan 6, 2021 at 7:20 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> > Hi,
> >
> > ping for code review? :)
> FWIW the full series (rebased on mips-next) is available here:
> https://gitlab.com/philmd/qemu/-/commits/mips_msa_decodetree

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

- Jiaxun

> > Due to the "Simplify ISA definitions"
> > https://www.mail-archive.com/qemu-devel@nongnu.org/msg770056.html
> > patch #3 is not necessary.
> >
> > This is the last patch unreviewed.
> >
> > On 12/15/20 11:57 PM, Philippe Mathieu-Daudé wrote:
> > > To allow compiling 64-bit specific translation code more
> > > generically (and removing #ifdef'ry), allow compiling
> > > check_mips_64() on 32-bit targets.
> > > If ever called on 32-bit, we obviously emit a reserved
> > > instruction exception.
> > >
> > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > > ---
> > >   target/mips/translate.h | 2 --
> > >   target/mips/translate.c | 8 +++-----
> > >   2 files changed, 3 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/target/mips/translate.h b/target/mips/translate.h
> > > index a9eab69249f..942d803476c 100644
> > > --- a/target/mips/translate.h
> > > +++ b/target/mips/translate.h
> > > @@ -127,9 +127,7 @@ void generate_exception_err(DisasContext *ctx, int excp, 
> > > int err);
> > >   void generate_exception_end(DisasContext *ctx, int excp);
> > >   void gen_reserved_instruction(DisasContext *ctx);
> > >   void check_insn(DisasContext *ctx, uint64_t flags);
> > > -#ifdef TARGET_MIPS64
> > >   void check_mips_64(DisasContext *ctx);
> > > -#endif
> > >   void check_cp1_enabled(DisasContext *ctx);
> > >
> > >   void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
> > > diff --git a/target/mips/translate.c b/target/mips/translate.c
> > > index 5c62b32c6ae..af543d1f375 100644
> > > --- a/target/mips/translate.c
> > > +++ b/target/mips/translate.c
> > > @@ -2972,18 +2972,16 @@ static inline void check_ps(DisasContext *ctx)
> > >       check_cp1_64bitmode(ctx);
> > >   }
> > >
> > > -#ifdef TARGET_MIPS64
> > >   /*
> > > - * This code generates a "reserved instruction" exception if 64-bit
> > > - * instructions are not enabled.
> > > + * This code generates a "reserved instruction" exception if cpu is not
> > > + * 64-bit or 64-bit instructions are not enabled.
> > >    */
> > >   void check_mips_64(DisasContext *ctx)
> > >   {
> > > -    if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
> > > +    if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
> > Since TARGET_LONG_BITS is known at build time, this can be simplified
> > as:
> >
> > if ((TARGET_LONG_BITS != 64) || unlikely!(ctx->hflags & MIPS_HFLAG_64)))
> >
> > >           gen_reserved_instruction(ctx);
> > >       }
> > >   }
> > > -#endif
> > >
> > >   #ifndef CONFIG_USER_ONLY
> > >   static inline void check_mvh(DisasContext *ctx)