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[PATCH 13/18] target/arm: generalize 2-stage page-walk condition
From: |
remi . denis . courmont |
Subject: |
[PATCH 13/18] target/arm: generalize 2-stage page-walk condition |
Date: |
Fri, 18 Dec 2020 12:37:54 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
The stage_1_mmu_idx() already effectively keeps track of which
translation regimes have two stages. Don't hard-code another test.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
target/arm/helper.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ff69b46d43..6d60fa23c9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12152,11 +12152,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong
address,
target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{
- if (mmu_idx == ARMMMUIdx_E10_0 ||
- mmu_idx == ARMMMUIdx_E10_1 ||
- mmu_idx == ARMMMUIdx_E10_1_PAN) {
+ ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
+
+ if (mmu_idx != s1_mmu_idx) {
/* Call ourselves recursively to do the stage 1 and then stage 2
- * translations.
+ * translations if mmu_idx is a two-stage regime.
*/
if (arm_feature(env, ARM_FEATURE_EL2)) {
hwaddr ipa;
@@ -12164,9 +12164,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong
address,
int ret;
ARMCacheAttrs cacheattrs2 = {};
- ret = get_phys_addr(env, address, access_type,
- stage_1_mmu_idx(mmu_idx), &ipa, attrs,
- prot, page_size, fi, cacheattrs);
+ ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
+ attrs, prot, page_size, fi, cacheattrs);
/* If S1 fails or S2 is disabled, return early. */
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
--
2.29.2
- [PATCH 02/18] target/arm: add arm_is_el2_enabled() helper, (continued)
- [PATCH 02/18] target/arm: add arm_is_el2_enabled() helper, remi . denis . courmont, 2020/12/18
- [PATCH 01/18] target/arm: remove redundant tests, remi . denis . courmont, 2020/12/18
- [PATCH 05/18] target/arm: factor MDCR_EL2 common handling, remi . denis . courmont, 2020/12/18
- [PATCH 03/18] target/arm: use arm_is_el2_enabled() where applicable, remi . denis . courmont, 2020/12/18
- [PATCH 06/18] target/arm: declare new AA64PFR0 bit-fields, remi . denis . courmont, 2020/12/18
- [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table, remi . denis . courmont, 2020/12/18
- [PATCH 04/18] target/arm: use arm_hcr_el2_eff() where applicable, remi . denis . courmont, 2020/12/18
- [PATCH 09/18] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2020/12/18
- [PATCH 10/18] target/arm: handle VMID change in secure state, remi . denis . courmont, 2020/12/18
- [PATCH 08/18] target/arm: add MMU stage 1 for Secure EL2, remi . denis . courmont, 2020/12/18
- [PATCH 13/18] target/arm: generalize 2-stage page-walk condition,
remi . denis . courmont <=
- [PATCH 15/18] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2020/12/18
- [PATCH 11/18] target/arm: do S1_ptw_translate() before address space lookup, remi . denis . courmont, 2020/12/18
- [PATCH 12/18] target/arm: translate NS bit in page-walks, remi . denis . courmont, 2020/12/18
- [PATCH 14/18] target/arm: secure stage 2 translation regime, remi . denis . courmont, 2020/12/18
- [PATCH 16/18] target/arm: add ARMv8.4-SEL2 extension, remi . denis . courmont, 2020/12/18
- [PATCH 18/18] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2020/12/18
- [PATCH 17/18] target/arm: enable Secure EL2 in max CPU, remi . denis . courmont, 2020/12/18