Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

[Atish Patra]

On Fri, 2020-12-18 at 15:21 +0800, Bin Meng wrote:
> Hi Atish,
> 
> On Fri, Dec 18, 2020 at 5:48 AM Atish Patra <atish.patra@wdc.com>
> wrote:
> > 
> > Currently, we place the DTB at 2MB from 4GB or end of DRAM which
> > ever is
> > lesser. However, Linux kernel can address only 1GB of memory for
> > RV32.
> > Thus, it can not map anything beyond 3GB (assuming 2GB is the
> > starting address).
> > As a result, it can not process DT and panic if opensbi dynamic
> > firmware
> > is used.
> > 
> > Fix this by placing the DTB at 2MB from 3GB or end of DRAM
> > whichever is lower.
> > 
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> >  hw/riscv/boot.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> 
> With this patch, 32-bit sifive_u still does not boot kernel with the
> following patch applied on 5.10:
> https://patchwork.kernel.org/project/linux-riscv/patch/20201217074855.1948743-1-atish.patra@wdc.com/
> 
> Command I used:
> $ qemu-system-riscv32 -nographic -M sifive_u -m 1G -smp 5 -kernel
> arch/riscv/boot/Image
> 
> 32-bit virt cannot boot the same kernel image with memory set to 2G
> either:
> $ qemu-system-riscv32 -nographic -M virt -m 2G -smp 4 -kernel
> arch/riscv/boot/Image
> 

Hi Bin,
As mentioned in the email on the linux mailing list, this patch only
solves 2GB problem. sifive_u problem is solved by Alistair's patch[1].

He is planning to send the PR soon. The issue with sifive_u boot was it
was failing the 32 bit test earlier resulting a 2MB aligned address
instead of 4MB.

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg767886.html

> Regards,
> Bin

-- 
Regards,
Atish