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[PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar r
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers |
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Date: |
Tue, 15 Dec 2020 23:57:42 +0100 |
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
It is not very clear to have FPU registers displayed with MSA
register names, even if MSA ASE is not present.
Instead of aliasing FPU registers to the MSA ones (even when MSA
is absent), we now alias the MSA ones to the FPU ones (only when
MSA is present).
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 02ea184f9a3..9b5b551b616 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31560,16 +31560,20 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
-
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
- msa_wr_d[i * 2] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
+
+ fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
+ }
+ /* MSA */
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
/*
- * The scalar floating-point unit (FPU) registers are mapped on
- * the MSA vector registers.
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
*/
- fpu_f64[i] = msa_wr_d[i * 2];
+ msa_wr_d[i * 2] = fpu_f64[i];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
--
2.26.2
- [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 05/24] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 07/24] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers,
Philippe Mathieu-Daudé <=
- [PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 11/24] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 13/24] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 14/24] target/mips: Move msa_reset() to mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 15/24] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 16/24] target/mips: Extract MSA helper definitions, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 17/24] target/mips: Declare gen_msa/_branch() in 'translate.h', Philippe Mathieu-Daudé, 2020/12/15