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Re: [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HE
From: |
Bin Meng |
Subject: |
Re: [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros |
Date: |
Tue, 15 Dec 2020 17:38:06 +0800 |
Hi Alistair,
On Tue, Dec 15, 2020 at 4:34 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The helper functions defined in helper.h specify that the argument is of
I can't find the helper.h that declare these functions?
> type target_long. Let's change the implementation to match the header
> definition.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/fpu_helper.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index bb346a8249..507d7fe7fa 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -224,13 +224,13 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env,
> uint64_t rs1)
> }
>
> #if defined(TARGET_RISCV64)
> -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
> +target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
> {
> float32 frs1 = check_nanbox_s(rs1);
> return float32_to_int64(frs1, &env->fp_status);
float32_to_int64() returns int64_t, so there is a truncation if
changing it to target_ulong for 32-bit.
> }
>
> -uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
> +target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
> {
> float32 frs1 = check_nanbox_s(rs1);
> return float32_to_uint64(frs1, &env->fp_status);
> @@ -248,12 +248,12 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env,
> target_ulong rs1)
> }
>
> #if defined(TARGET_RISCV64)
> -uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
> +uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
> {
> return nanbox_s(int64_to_float32(rs1, &env->fp_status));
> }
>
> -uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
> +uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
> {
> return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
> }
> @@ -337,12 +337,12 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env,
> uint64_t frs1)
> }
>
> #if defined(TARGET_RISCV64)
> -uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
> +target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
> {
> return float64_to_int64(frs1, &env->fp_status);
> }
>
> -uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
> +target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
> {
> return float64_to_uint64(frs1, &env->fp_status);
> }
> @@ -359,12 +359,12 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env,
> target_ulong rs1)
> }
>
> #if defined(TARGET_RISCV64)
> -uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
> +uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
> {
> return int64_to_float64(rs1, &env->fp_status);
> }
>
> -uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
> +uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
> {
> return uint64_to_float64(rs1, &env->fp_status);
> }
Regards,
Bin
- Re: [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs, (continued)
- [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/14
- [PATCH v3 03/15] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/14
- [PATCH v3 04/15] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/14
- [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 06/15] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 07/15] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 08/15] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/14
- Re: [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros,
Bin Meng <=
- [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/14
- [PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/14
- [PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 13/15] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 14/15] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target, Alistair Francis, 2020/12/14