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[PATCH v4 38/43] tcg/mips: Do not assert on relocation overflow
From: |
Richard Henderson |
Subject: |
[PATCH v4 38/43] tcg/mips: Do not assert on relocation overflow |
Date: |
Mon, 14 Dec 2020 08:03:09 -0600 |
This target was not updated with 7ecd02a06f8, and so did
not allow re-compilation with relocation overflow.
Remove reloc_26 and reloc_26_val as unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 53 ++++++++++++++-------------------------
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 52638e920c..37faf1356c 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -144,29 +144,15 @@ static tcg_insn_unit *bswap32_addr;
static tcg_insn_unit *bswap32u_addr;
static tcg_insn_unit *bswap64_addr;
-static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc,
- const tcg_insn_unit *target)
+static bool reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target)
{
/* Let the compiler perform the right-shift as part of the arithmetic. */
ptrdiff_t disp = target - (pc + 1);
- tcg_debug_assert(disp == (int16_t)disp);
- return disp & 0xffff;
-}
-
-static inline void reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target)
-{
- *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
-}
-
-static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
- return ((uintptr_t)target >> 2) & 0x3ffffff;
-}
-
-static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
+ if (disp == (int16_t)disp) {
+ *pc = deposit32(*pc, 0, 16, disp);
+ return true;
+ }
+ return false;
}
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
@@ -174,8 +160,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
{
tcg_debug_assert(type == R_MIPS_PC16);
tcg_debug_assert(addend == 0);
- reloc_pc16(code_ptr, (tcg_insn_unit *)value);
- return true;
+ return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
}
#define TCG_CT_CONST_ZERO 0x100
@@ -925,11 +910,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond,
TCGReg arg1,
}
tcg_out_opc_br(s, b_opc, arg1, arg2);
- if (l->has_value) {
- reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
- } else {
- tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
- }
+ tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
tcg_out_nop(s);
}
@@ -1316,9 +1297,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
int i;
/* resolve label address */
- reloc_pc16(l->label_ptr[0], s->code_ptr);
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- reloc_pc16(l->label_ptr[1], s->code_ptr);
+ if (!reloc_pc16(l->label_ptr[0], s->code_ptr)
+ || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
+ && !reloc_pc16(l->label_ptr[1], s->code_ptr))) {
+ return false;
}
i = 1;
@@ -1346,7 +1328,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
}
tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
- reloc_pc16(s->code_ptr - 1, l->raddr);
+ if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
+ return false;
+ }
/* delay slot */
if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
@@ -1366,9 +1350,10 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
int i;
/* resolve label address */
- reloc_pc16(l->label_ptr[0], s->code_ptr);
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- reloc_pc16(l->label_ptr[1], s->code_ptr);
+ if (!reloc_pc16(l->label_ptr[0], s->code_ptr)
+ || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
+ && !reloc_pc16(l->label_ptr[1], s->code_ptr))) {
+ return false;
}
i = 1;
--
2.25.1
- [PATCH v4 23/43] tcg/aarch64: Support split-wx code generation, (continued)
- [PATCH v4 23/43] tcg/aarch64: Support split-wx code generation, Richard Henderson, 2020/12/14
- [PATCH v4 31/43] tcg/sparc: Support split-wx code generation, Richard Henderson, 2020/12/14
- [PATCH v4 32/43] tcg/s390: Use tcg_tbrel_diff, Richard Henderson, 2020/12/14
- [PATCH v4 33/43] tcg/s390: Support split-wx code generation, Richard Henderson, 2020/12/14
- [PATCH v4 35/43] tcg/riscv: Remove branch-over-branch fallback, Richard Henderson, 2020/12/14
- [PATCH v4 36/43] tcg/riscv: Support split-wx code generation, Richard Henderson, 2020/12/14
- [PATCH v4 37/43] accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd, Richard Henderson, 2020/12/14
- [PATCH v4 42/43] tcg: Constify tcg_code_gen_epilogue, Richard Henderson, 2020/12/14
- [PATCH v4 38/43] tcg/mips: Do not assert on relocation overflow,
Richard Henderson <=
- [PATCH v4 34/43] tcg/riscv: Fix branch range checks, Richard Henderson, 2020/12/14
- [PATCH v4 40/43] tcg/arm: Support split-wx code generation, Richard Henderson, 2020/12/14
- [PATCH v4 39/43] tcg/mips: Support split-wx code generation, Richard Henderson, 2020/12/14
- [PATCH v4 41/43] tcg: Remove TCG_TARGET_SUPPORT_MIRROR, Richard Henderson, 2020/12/14
- [PATCH v4 43/43] tcg: Constify TCGLabelQemuLdst.raddr, Richard Henderson, 2020/12/14
- Re: [PATCH v4 00/43] Mirror map JIT memory for TCG, no-reply, 2020/12/14