Re: [PATCH 26/26] MAINTAINERS: Add entry for MIPS Toshiba TCG

[Fredrik Noring]

On Fri, Nov 20, 2020 at 10:08:44PM +0100, Philippe Mathieu-Daudé wrote:
> Add an entry for the TCG core related to Toshiba TXx9.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Adding Fredrik Noring in case he wants to be notified of changes,
> patch conditional to his approval.

I may be able to help on the TX79 that is an R5900, but unless commit
823f2897bdd7 ("target/mips: Disable R5900 support") is reverted, it
remains shut off in QEMU. To obtain n32, in addition to o32, one may
want to apply something similar to this:

diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h
index ec55d8542a..5f2f2df29f 100644
--- a/linux-user/mips64/target_elf.h
+++ b/linux-user/mips64/target_elf.h
@@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags)
     if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) {
         return "I6400";
     }
+    if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) {
+        return "R5900";
+    }
     return "5KEf";
 }
 #endif

> ---
>  MAINTAINERS | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b6d98b95c47..d97f0f1d66e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -253,6 +253,12 @@ R: Craig Janeczek <jancraig@amazon.com>
>  S: Odd Fixes
>  F: target/mips/vendor-xburst*
>  
> +MIPS TCG CPUs (Toshiba TX)
> +M: Philippe Mathieu-Daudé <f4bug@amsat.org>
> +R: Fredrik Noring <noring@nocrew.org>
> +S: Odd Fixes
> +F: target/mips/vendor-tx*
> +
>  MIPS TCG CPUs (nanoMIPS ISA)
>  S: Orphan
>  F: disas/nanomips.*
> -- 
> 2.26.2
> 

Fredrik