Re: [RFC PATCH] hw/misc/zynq_slcr: Avoid #DIV/0! error

[Edgar E. Iglesias]

On Thu, Dec 10, 2020 at 08:39:32AM -0800, Alistair Francis wrote:
> On Thu, Dec 10, 2020 at 6:27 AM Philippe Mathieu-Daudé <f4bug@amsat.org> 
> wrote:
> >
> > Malicious user can set the feedback divisor for the PLLs
> > to zero, triggering a floating-point exception (SIGFPE).
> >
> > As the datasheet [*] is not clear how hardware behaves
> > when these bits are zeroes, use the maximum divisor
> > possible (128) to avoid the software FPE.
> >
> > [*] Zynq-7000 TRM, UG585 (v1.12.2)
> >     B.28 System Level Control Registers (slcr)
> >     -> "Register (slcr) ARM_PLL_CTRL"
> >     25.10.4 PLLs
> >     -> "Software-Controlled PLL Update"
> >
> > Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts")
> > Reported-by: Gaoning Pan <pgn@zju.edu.cn>
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > ---
> > Cc: Damien Hedde <damien.hedde@greensocs.com>
> > Cc: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > Cc: Alistair Francis <alistair.francis@wdc.com>
> > Cc: Gaoning Pan <gaoning.pgn@antgroup.com>
> > Cc: Mauro Matteo Cascella <mcascell@redhat.com>
> >
> > Alternative is to threat that as PLL disabled and return 0...
> 
> I'm not sure which is better, but this patch now is better then before:
> 
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

I agree with Alistair:

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>