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[PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc
From: |
Peter Maydell |
Subject: |
[PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc |
Date: |
Thu, 10 Dec 2020 11:47:41 +0000 |
v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
like the existing FPSCR, except that it reads and writes only bits
[31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the
FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
permitted.)
Implement the register. Since we don't yet implement MVE, we handle
the QC bit as RES0, with todo comments for where we will need to add
support later.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-11-peter.maydell@linaro.org
---
target/arm/cpu.h | 13 +++++++++++++
target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ad8b80c667d..04f6220b2f7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1524,6 +1524,13 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
+#define FPCR_V (1 << 28) /* FP overflow flag */
+#define FPCR_C (1 << 29) /* FP carry flag */
+#define FPCR_Z (1 << 30) /* FP zero flag */
+#define FPCR_N (1 << 31) /* FP negative flag */
+
+#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
+#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
static inline uint32_t vfp_get_fpsr(CPUARMState *env)
{
@@ -1568,6 +1575,12 @@ enum arm_cpu_mode {
#define ARM_VFP_FPEXC 8
#define ARM_VFP_FPINST 9
#define ARM_VFP_FPINST2 10
+/* These ones are M-profile only */
+#define ARM_VFP_FPSCR_NZCVQC 2
+#define ARM_VFP_VPR 12
+#define ARM_VFP_P0 13
+#define ARM_VFP_FPCXT_NS 14
+#define ARM_VFP_FPCXT_S 15
/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
#define QEMU_VFP_FPSCR_NZCV 0xffff
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index f884d680a03..d698f3e1cd1 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -648,6 +648,11 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext
*s, int regno)
case ARM_VFP_FPSCR:
case QEMU_VFP_FPSCR_NZCV:
break;
+ case ARM_VFP_FPSCR_NZCVQC:
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+ return false;
+ }
+ break;
default:
return FPSysRegCheckFailed;
}
@@ -683,6 +688,22 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int
regno,
tcg_temp_free_i32(tmp);
gen_lookup_tb(s);
break;
+ case ARM_VFP_FPSCR_NZCVQC:
+ {
+ TCGv_i32 fpscr;
+ tmp = loadfn(s, opaque);
+ /*
+ * TODO: when we implement MVE, write the QC bit.
+ * For non-MVE, QC is RES0.
+ */
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
+ fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
+ tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
+ tcg_gen_or_i32(fpscr, fpscr, tmp);
+ store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
+ tcg_temp_free_i32(tmp);
+ break;
+ }
default:
g_assert_not_reached();
}
@@ -711,6 +732,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int
regno,
gen_helper_vfp_get_fpscr(tmp, cpu_env);
storefn(s, opaque, tmp);
break;
+ case ARM_VFP_FPSCR_NZCVQC:
+ /*
+ * TODO: MVE has a QC bit, which we probably won't store
+ * in the xregs[] field. For non-MVE, where QC is RES0,
+ * we can just fall through to the FPSCR_NZCV case.
+ */
case QEMU_VFP_FPSCR_NZCV:
/*
* Read just NZCV; this is a special case to avoid the
--
2.20.1
- [PULL 09/36] i.MX31: Fix bad printf format specifiers, (continued)
- [PULL 09/36] i.MX31: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure, Peter Maydell, 2020/12/10
- [PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/12/10
- [PULL 08/36] i.MX25: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 10/36] i.MX6: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 16/36] target/arm: Implement CLRM instruction, Peter Maydell, 2020/12/10
- [PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/12/10
- [PULL 11/36] i.MX6ul: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 13/36] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/12/10
- [PULL 15/36] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/12/10
- [PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc,
Peter Maydell <=
- [PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M, Peter Maydell, 2020/12/10
- [PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant, Peter Maydell, 2020/12/10
- [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/12/10
- [PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/12/10
- [PULL 28/36] target/arm: Implement v8.1M REVIDR register, Peter Maydell, 2020/12/10
- [PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry, Peter Maydell, 2020/12/10
- [PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings, Peter Maydell, 2020/12/10
- [PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation", Peter Maydell, 2020/12/10
- [PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/12/10
- [PULL 20/36] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/12/10