[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v2 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU |
|
Date: |
Tue, 8 Dec 2020 14:56:14 -0800 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
target/riscv/cpu.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c0a326c843..9c064f3094 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -44,6 +44,12 @@
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#if defined(TARGET_RISCV32)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
+#elif defined(TARGET_RISCV64)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
+#endif
+
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
--
2.29.2
- [PATCH v2 00/15] RISC-V: Start to remove xlen preprocess, Alistair Francis, 2020/12/08
- [PATCH v2 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/08
- [PATCH v2 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU,
Alistair Francis <=
- [PATCH v2 03/15] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/08
- [PATCH v2 04/15] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/08
- [PATCH v2 05/15] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
- [PATCH v2 06/15] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
- [PATCH v2 07/15] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
- [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/08