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Re: [PATCH] target/mips: Allow executing MSA instructions on Loongson-3A
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH] target/mips: Allow executing MSA instructions on Loongson-3A4000 |
Date: |
Mon, 7 Dec 2020 23:27:34 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 |
On 11/30/20 11:22 AM, Philippe Mathieu-Daudé wrote:
> The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html
>
> Commit af868995e1b correctly set the 'MSA present' bit of Config3
> register, but forgot to allow the MSA instructions decoding in
> insn_flags, so executing them triggers a 'Reserved Instruction'.
>
> Fix by adding the ASE_MSA mask to insn_flags.
>
> Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Buggy since 5.1, so probably not a big deal.
> ---
> target/mips/translate_init.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Thanks, applied to mips-next.