Re: [PATCH 2/5] hw/mips/malta: Make use of bootloader helper

[Philippe Mathieu-Daudé]

On 12/7/20 6:02 AM, Jiaxun Yang wrote:
> Use bootloader helper to generate BAR setting code
> and kernel jump.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  hw/mips/malta.c | 108 ++++++++++++------------------------------------
>  1 file changed, 26 insertions(+), 82 deletions(-)
> 
...
> +    /* GT64xxxx is always big endian */
>  #ifdef TARGET_WORDS_BIGENDIAN
> -    stl_p(p++, 0x3c08c100);                  /* lui t0, 0xc100 */
> +#define cpu_to_gt32(x) cpu_to_le32(x)
>  #else
> -    stl_p(p++, 0x340800c1);                  /* ori t0, r0, 0x00c1 */
> +#define cpu_to_gt32(x) cpu_to_be32(x)
>  #endif
> -    stl_p(p++, 0xad280080);                  /* sw t0, 0x0080(t1) */
> -#ifdef TARGET_WORDS_BIGENDIAN
> -    stl_p(p++, 0x3c085e00);                  /* lui t0, 0x5e00 */
> -#else
> -    stl_p(p++, 0x3408005e);                  /* ori t0, r0, 0x005e */
> -#endif
> -    stl_p(p++, 0xad280088);                  /* sw t0, 0x0088(t1) */
> +    /* Load BAR registers as done by YAMON */
> +    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
> +    bl_gen_writel(&p, cpu_to_gt32(0xdf000000), 0xb4000068);

Ideally we'd write as:

    bl_gen_writel(&p, cpu_to_be32(0x1be00000 << 3),
                  cpu_mips_phys_to_kseg1(NULL, 0x14000068));

But I guess this is enough:

    bl_gen_writel(&p, cpu_to_be32(0x1be00000 << 3), 0xb4000068);

No need for cpu_to_gt32().

>From a review point of view, it would be easier to split your
patches in 2: first use bl_gen_write_u32/u64, second convert
bl_gen_jump_to_u32 and bl_gen_jump_kernel_u32.

> +
> +    /* setup MEM-to-PCI0 mapping */
> +    /* setup PCI0 io window to 0x18000000-0x181fffff */
> +    bl_gen_writel(&p, cpu_to_gt32(0xc0000000), 0xbbe00048);
> +    bl_gen_writel(&p, cpu_to_gt32(0x40000000), 0xbbe00050);
> +    /* setup PCI0 mem windows */
> +    bl_gen_writel(&p, cpu_to_gt32(0x80000000), 0xbbe00058);
> +    bl_gen_writel(&p, cpu_to_gt32(0x3f000000), 0xbbe00060);
> +    bl_gen_writel(&p, cpu_to_gt32(0xc1000000), 0xbbe00080);
> +    bl_gen_writel(&p, cpu_to_gt32(0x5e000000), 0xbbe00088);
> +#undef cpu_to_gt32
>  
> -    /* Jump to kernel code */
> -    stl_p(p++, 0x3c1f0000 |
> -          ((kernel_entry >> 16) & 0xffff));  /* lui ra, high(kernel_entry) */
> -    stl_p(p++, 0x37ff0000 |
> -          (kernel_entry & 0xffff));          /* ori ra, ra, 
> low(kernel_entry) */
> -    stl_p(p++, 0x03e00009);                  /* jalr ra */
> -    stl_p(p++, 0x00000000);                  /* nop */
> +    if (semihosting_get_argc()) {
> +        a0 = 0;
> +    } else {
> +        a0 = 2;
> +    }
> +    bl_gen_jump_kernel(&p, ENVP_ADDR - 64, a0, ENVP_ADDR, (ENVP_ADDR + 8),
> +                        loaderparams.ram_low_size, kernel_entry);
>  
>      /* YAMON subroutines */
>      p = (uint32_t *) (base + 0x800);
>