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[PULL 020/113] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
From: |
Paolo Bonzini |
Subject: |
[PULL 020/113] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink |
Date: |
Wed, 2 Dec 2020 03:07:16 -0500 |
From: Philippe Mathieu-Daudé <philmd@redhat.com>
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20200910070131.435543-5-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/net/xilinx_axienet.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 9bccbe9be3..990ff3a1c2 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -45,11 +45,11 @@
OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET)
-typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
-DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_DATA_STREAM,
+typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
+DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_DATA_STREAM,
TYPE_XILINX_AXI_ENET_DATA_STREAM)
-DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave,
XILINX_AXI_ENET_CONTROL_STREAM,
+DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink,
XILINX_AXI_ENET_CONTROL_STREAM,
TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
/* Advertisement control register. */
@@ -310,7 +310,7 @@ struct TEMAC {
};
-struct XilinxAXIEnetStreamSlave {
+struct XilinxAXIEnetStreamSink {
Object parent;
struct XilinxAXIEnet *enet;
@@ -322,8 +322,8 @@ struct XilinxAXIEnet {
qemu_irq irq;
StreamSink *tx_data_dev;
StreamSink *tx_control_dev;
- XilinxAXIEnetStreamSlave rx_data_dev;
- XilinxAXIEnetStreamSlave rx_control_dev;
+ XilinxAXIEnetStreamSink rx_data_dev;
+ XilinxAXIEnetStreamSink rx_control_dev;
NICState *nic;
NICConf conf;
@@ -856,7 +856,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t
*buf, size_t len,
bool eop)
{
int i;
- XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
+ XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
XilinxAXIEnet *s = cs->enet;
assert(eop);
@@ -877,7 +877,7 @@ static size_t
xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
bool eop)
{
- XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
+ XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
XilinxAXIEnet *s = ds->enet;
/* TX enable ? */
@@ -951,8 +951,8 @@ static NetClientInfo net_xilinx_enet_info = {
static void xilinx_enet_realize(DeviceState *dev, Error **errp)
{
XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
- XilinxAXIEnetStreamSlave *ds =
XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
- XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
+ XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
+ XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
&s->rx_control_dev);
object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
@@ -1043,7 +1043,7 @@ static const TypeInfo xilinx_enet_info = {
static const TypeInfo xilinx_enet_data_stream_info = {
.name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(XilinxAXIEnetStreamSlave),
+ .instance_size = sizeof(XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_data_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
@@ -1054,7 +1054,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
static const TypeInfo xilinx_enet_control_stream_info = {
.name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(XilinxAXIEnetStreamSlave),
+ .instance_size = sizeof(XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_control_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
--
2.26.2
- [PULL 006/113] qom: eliminate identical functions, (continued)
- [PULL 006/113] qom: eliminate identical functions, Paolo Bonzini, 2020/12/02
- [PULL 012/113] pci: Let pci_dma_rw() propagate MemTxResult, Paolo Bonzini, 2020/12/02
- [PULL 010/113] dma: Let dma_memory_read() propagate MemTxResult, Paolo Bonzini, 2020/12/02
- [PULL 011/113] dma: Let dma_memory_write() propagate MemTxResult, Paolo Bonzini, 2020/12/02
- [PULL 015/113] hw/ssi/aspeed_smc: Rename 'max_slaves' variable as 'max_peripherals', Paolo Bonzini, 2020/12/02
- [PULL 019/113] hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink, Paolo Bonzini, 2020/12/02
- [PULL 022/113] arm: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 021/113] alpha: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 024/113] i386: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 025/113] lm32: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 020/113] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink,
Paolo Bonzini <=
- [PULL 027/113] mips: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 018/113] hw/core/stream: Rename StreamSlave as StreamSink, Paolo Bonzini, 2020/12/02
- [PULL 016/113] hw/ssi: Update coding style to make checkpatch.pl happy, Paolo Bonzini, 2020/12/02
- [PULL 028/113] moxie: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 017/113] hw/ssi: Rename SSI 'slave' as 'peripheral', Paolo Bonzini, 2020/12/02
- [PULL 023/113] hppa: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 026/113] m68k: remove bios_name, Paolo Bonzini, 2020/12/02
- [PULL 030/113] rx: move BIOS load from MCU to board, Paolo Bonzini, 2020/12/02
- [PULL 037/113] cris: do not use ram_size global, Paolo Bonzini, 2020/12/02
- [PULL 031/113] s390: remove bios_name, Paolo Bonzini, 2020/12/02