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[PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table
From: |
remi . denis . courmont |
Subject: |
[PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table |
Date: |
Mon, 23 Nov 2020 10:02:27 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in
secure mode, though it can only be AArch64.
This patch adds the target EL for exceptions from 64-bit S-EL2.
It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure
mode. Those values were never used in practice as the effective value of
HCR was always 0 in secure mode.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
target/arm/helper.c | 10 +++++-----
target/arm/op_helper.c | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e55059585b..a69fde826b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9005,13 +9005,13 @@ static const int8_t target_el_table[2][2][2][2][2][4] =
{
{{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
{/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
{{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
- {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
- {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
- {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
+ {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
+ {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
+ {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
{{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
{/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
- {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
- {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
+ {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
+ {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
};
/*
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index ff91fe6121..5e0f123043 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -652,10 +652,10 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void
*rip, uint32_t syndrome,
target_el = exception_target_el(env);
break;
case CP_ACCESS_TRAP_EL2:
- /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
+ /* Requesting a trap to EL2 when we're in EL3 is
* a bug in the access function.
*/
- assert(!arm_is_secure(env) && arm_current_el(env) != 3);
+ assert(arm_current_el(env) != 3);
target_el = 2;
break;
case CP_ACCESS_TRAP_EL3:
--
2.29.2
- [PATCHv3 00/17] ARMv8.4 Secure EL2, Rémi Denis-Courmont, 2020/11/23
- [PATCH 01/17] target/arm: remove redundant tests, remi . denis . courmont, 2020/11/23
- [PATCH 04/17] target/arm: use arm_hcr_el2_eff() where applicable, remi . denis . courmont, 2020/11/23
- [PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table,
remi . denis . courmont <=
- [PATCH 05/17] target/arm: factor MDCR_EL2 common handling, remi . denis . courmont, 2020/11/23
- [PATCH 02/17] target/arm: add arm_is_el2_enabled() helper, remi . denis . courmont, 2020/11/23
- [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable, remi . denis . courmont, 2020/11/23
- [PATCH 08/17] target/arm: return the stage 2 index for stage 1, remi . denis . courmont, 2020/11/23
- [PATCH 10/17] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2020/11/23
- [PATCH 09/17] target/arm: add MMU stage 1 for Secure EL2, remi . denis . courmont, 2020/11/23
- [PATCH 06/17] target/arm: declare new AA64PFR0 bit-fields, remi . denis . courmont, 2020/11/23
- [PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2020/11/23
- [PATCH 17/17] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2020/11/23
- [PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup, remi . denis . courmont, 2020/11/23