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Re: [RFC 05/15] target/riscv: rvb: pack two words into one register
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From: |
Richard Henderson |
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Subject: |
Re: [RFC 05/15] target/riscv: rvb: pack two words into one register |
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Date: |
Thu, 19 Nov 2020 11:43:52 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> + tcg_gen_ext32u_tl(lower, arg1);
> + tcg_gen_shli_tl(higher, arg2, 32);
> +#else
> + tcg_gen_ext16u_tl(lower, arg1);
> + tcg_gen_shli_tl(higher, arg2, 16);
> +#endif
> +
tcg_gen_deposit(ret, arg1, arg2,
TARGET_LONG_BITS / 2,
TARGET_LONG_BITS / 2);
> +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> + tcg_gen_shri_tl(lower, arg1, 32);
> + tcg_gen_shri_tl(higher, arg2, 32);
> + tcg_gen_shli_tl(higher, higher, 32);
> +#else
> + tcg_gen_shri_tl(lower, arg1, 16);
> + tcg_gen_shri_tl(higher, arg2, 16);
> + tcg_gen_shli_tl(higher, higher, 16);
> +#endif
> +
> + tcg_gen_or_tl(ret, higher, lower);
tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
> +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> + tcg_gen_ext8u_tl(lower, arg1);
> + tcg_gen_ext8u_tl(higher, arg2);
> + tcg_gen_shli_tl(higher, higher, 8);
> +
> + tcg_gen_or_tl(ret, higher, lower);
tcg_gen_ext8u_tl(t, arg2);
tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
> +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> + tcg_gen_ext16u_tl(lower, arg1);
> + tcg_gen_shli_tl(higher, arg2, 16);
> + tcg_gen_or_tl(ret, higher, lower);
> +
> + tcg_gen_ext32s_tl(ret, ret);
> +
> + tcg_temp_free(lower);
> + tcg_temp_free(higher);
> +}
tcg_gen_ext16s_i64(t, arg2);
tcg_gen_deposit_i64(ret, arg1, t, 16, 48);
> +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> + tcg_gen_shri_tl(lower, arg1, 16);
> + tcg_gen_shri_tl(higher, arg2, 16);
> + tcg_gen_shli_tl(higher, higher, 16);
> + tcg_gen_or_tl(ret, higher, lower);
> +
> + tcg_gen_ext32s_tl(ret, ret);
tcg_gen_shri_i64(t, arg1, 16);
tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
tcg_gen_ext32s_i64(ret, ret);
r~
- [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension, (continued)
- [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2020/11/18
- [RFC 02/15] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2020/11/18
- [RFC 03/15] target/riscv: rvb: count bits set, frank . chang, 2020/11/18
- [RFC 04/15] target/riscv: rvb: logic-with-negate, frank . chang, 2020/11/18
- [RFC 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/11/18
- Re: [RFC 05/15] target/riscv: rvb: pack two words into one register,
Richard Henderson <=
- [RFC 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/11/18
- [RFC 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/11/18
- [RFC 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/11/18
- [RFC 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/11/18