[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PULL 0/6] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
Re: [PULL 0/6] riscv-to-apply queue |
Date: |
Mon, 9 Nov 2020 20:00:26 -0800 |
On Mon, Nov 9, 2020 at 8:09 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The following changes since commit 3c8c36c9087da957f580a9bb5ebf7814a753d1c6:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201104-pull-request'
> into staging (2020-11-04 16:52:17 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201109
>
> for you to fetch changes up to 96338fefc19a143abdc91f6c44f37683274b08d4:
>
> hw/intc/ibex_plic: Clear the claim register when read (2020-11-09 15:09:53
> -0800)
>
> ----------------------------------------------------------------
> This fixes two bugs in the RISC-V port. One is a bug in the
> Ibex PLIC, the other fixes the Hypvervisor access functions.
>
> ----------------------------------------------------------------
> Alistair Francis (6):
> target/riscv: Add a virtualised MMU Mode
> target/riscv: Set the virtualised MMU mode when doing hyp accesses
> target/riscv: Remove the HS_TWO_STAGE flag
> target/riscv: Remove the hyp load and store functions
> target/riscv: Split the Hypervisor execute load helpers
> hw/intc/ibex_plic: Clear the claim register when read
Just a note, the hypervisor related changes look like a big diff for
this late in the cycle. That is true, but the current implementation
(added in this release cycle) is broken and this fixes it. Also most
of the changes only affect the Hypervisor extensions, which are still
experiemental.
Alistair
>
> target/riscv/cpu-param.h | 11 ++-
> target/riscv/cpu.h | 19 ++++-
> target/riscv/cpu_bits.h | 1 -
> target/riscv/helper.h | 5 +-
> hw/intc/ibex_plic.c | 3 +
> target/riscv/cpu_helper.c | 62 ++++++--------
> target/riscv/op_helper.c | 124 ++-------------------------
> target/riscv/translate.c | 2 +
> target/riscv/insn_trans/trans_rvh.c.inc | 143
> ++++++++++++--------------------
> 9 files changed, 115 insertions(+), 255 deletions(-)
- [PULL 0/6] riscv-to-apply queue, Alistair Francis, 2020/11/09
- [PULL 1/6] target/riscv: Add a virtualised MMU Mode, Alistair Francis, 2020/11/09
- [PULL 2/6] target/riscv: Set the virtualised MMU mode when doing hyp accesses, Alistair Francis, 2020/11/09
- [PULL 3/6] target/riscv: Remove the HS_TWO_STAGE flag, Alistair Francis, 2020/11/09
- [PULL 4/6] target/riscv: Remove the hyp load and store functions, Alistair Francis, 2020/11/09
- [PULL 5/6] target/riscv: Split the Hypervisor execute load helpers, Alistair Francis, 2020/11/09
- [PULL 6/6] hw/intc/ibex_plic: Clear the claim register when read, Alistair Francis, 2020/11/09
- Re: [PULL 0/6] riscv-to-apply queue,
Alistair Francis <=
- Re: [PULL 0/6] riscv-to-apply queue, Peter Maydell, 2020/11/10