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[RFC PATCH v5 16/33] Hexagon (target/hexagon/conv_emu.[ch]) utility func
From: |
Taylor Simpson |
Subject: |
[RFC PATCH v5 16/33] Hexagon (target/hexagon/conv_emu.[ch]) utility functions |
Date: |
Thu, 29 Oct 2020 19:08:22 -0500 |
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/conv_emu.h | 31 ++++++++
target/hexagon/conv_emu.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 208 insertions(+)
create mode 100644 target/hexagon/conv_emu.h
create mode 100644 target/hexagon/conv_emu.c
diff --git a/target/hexagon/conv_emu.h b/target/hexagon/conv_emu.h
new file mode 100644
index 0000000..d05e7cc
--- /dev/null
+++ b/target/hexagon/conv_emu.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_CONV_EMU_H
+#define HEXAGON_CONV_EMU_H
+
+extern uint64_t conv_sf_to_8u(float32 in, float_status *fp_status);
+extern uint32_t conv_sf_to_4u(float32 in, float_status *fp_status);
+extern int64_t conv_sf_to_8s(float32 in, float_status *fp_status);
+extern int32_t conv_sf_to_4s(float32 in, float_status *fp_status);
+
+extern uint64_t conv_df_to_8u(float64 in, float_status *fp_status);
+extern uint32_t conv_df_to_4u(float64 in, float_status *fp_status);
+extern int64_t conv_df_to_8s(float64 in, float_status *fp_status);
+extern int32_t conv_df_to_4s(float64 in, float_status *fp_status);
+
+#endif
diff --git a/target/hexagon/conv_emu.c b/target/hexagon/conv_emu.c
new file mode 100644
index 0000000..b09ea63
--- /dev/null
+++ b/target/hexagon/conv_emu.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "fpu/softfloat.h"
+#include "macros.h"
+#include "conv_emu.h"
+
+#define LL_MAX_POS 0x7fffffffffffffffULL
+#define MAX_POS 0x7fffffffU
+
+static uint64_t conv_f64_to_8u_n(float64 in, int will_negate,
+ float_status *fp_status)
+{
+ uint8_t sign = float64_is_neg(in);
+ if (float64_is_infinity(in)) {
+ float_raise(float_flag_invalid, fp_status);
+ if (float64_is_neg(in)) {
+ return 0ULL;
+ } else {
+ return ~0ULL;
+ }
+ }
+ if (float64_is_any_nan(in)) {
+ float_raise(float_flag_invalid, fp_status);
+ return ~0ULL;
+ }
+ if (float64_is_zero(in)) {
+ return 0;
+ }
+ if (sign) {
+ float_raise(float_flag_invalid, fp_status);
+ return 0;
+ }
+ if (float64_lt(in, float64_half, fp_status)) {
+ /* Near zero, captures large fracshifts, denorms, etc */
+ float_raise(float_flag_inexact, fp_status);
+ switch (get_float_rounding_mode(fp_status)) {
+ case float_round_down:
+ if (will_negate) {
+ return 1;
+ } else {
+ return 0;
+ }
+ case float_round_up:
+ if (!will_negate) {
+ return 1;
+ } else {
+ return 0;
+ }
+ default:
+ return 0; /* nearest or towards zero */
+ }
+ }
+ return float64_to_uint64(in, fp_status);
+}
+
+static void clr_float_exception_flags(uint8_t flag, float_status *fp_status)
+{
+ uint8_t flags = fp_status->float_exception_flags;
+ flags &= ~flag;
+ set_float_exception_flags(flags, fp_status);
+}
+
+static uint32_t conv_df_to_4u_n(float64 fp64, int will_negate,
+ float_status *fp_status)
+{
+ uint64_t tmp;
+ tmp = conv_f64_to_8u_n(fp64, will_negate, fp_status);
+ if (tmp > 0x00000000ffffffffULL) {
+ clr_float_exception_flags(float_flag_inexact, fp_status);
+ float_raise(float_flag_invalid, fp_status);
+ return ~0U;
+ }
+ return (uint32_t)tmp;
+}
+
+uint64_t conv_df_to_8u(float64 in, float_status *fp_status)
+{
+ return conv_f64_to_8u_n(in, 0, fp_status);
+}
+
+uint32_t conv_df_to_4u(float64 in, float_status *fp_status)
+{
+ return conv_df_to_4u_n(in, 0, fp_status);
+}
+
+int64_t conv_df_to_8s(float64 in, float_status *fp_status)
+{
+ uint8_t sign = float64_is_neg(in);
+ uint64_t tmp;
+ if (float64_is_any_nan(in)) {
+ float_raise(float_flag_invalid, fp_status);
+ return -1;
+ }
+ if (sign) {
+ float64 minus_fp64 = float64_abs(in);
+ tmp = conv_f64_to_8u_n(minus_fp64, 1, fp_status);
+ } else {
+ tmp = conv_f64_to_8u_n(in, 0, fp_status);
+ }
+ if (tmp > (LL_MAX_POS + sign)) {
+ clr_float_exception_flags(float_flag_inexact, fp_status);
+ float_raise(float_flag_invalid, fp_status);
+ tmp = (LL_MAX_POS + sign);
+ }
+ if (sign) {
+ return -tmp;
+ } else {
+ return tmp;
+ }
+}
+
+int32_t conv_df_to_4s(float64 in, float_status *fp_status)
+{
+ uint8_t sign = float64_is_neg(in);
+ uint64_t tmp;
+ if (float64_is_any_nan(in)) {
+ float_raise(float_flag_invalid, fp_status);
+ return -1;
+ }
+ if (sign) {
+ float64 minus_fp64 = float64_abs(in);
+ tmp = conv_f64_to_8u_n(minus_fp64, 1, fp_status);
+ } else {
+ tmp = conv_f64_to_8u_n(in, 0, fp_status);
+ }
+ if (tmp > (MAX_POS + sign)) {
+ clr_float_exception_flags(float_flag_inexact, fp_status);
+ float_raise(float_flag_invalid, fp_status);
+ tmp = (MAX_POS + sign);
+ }
+ if (sign) {
+ return -tmp;
+ } else {
+ return tmp;
+ }
+}
+
+uint64_t conv_sf_to_8u(float32 in, float_status *fp_status)
+{
+ float64 fp64 = float32_to_float64(in, fp_status);
+ return conv_df_to_8u(fp64, fp_status);
+}
+
+uint32_t conv_sf_to_4u(float32 in, float_status *fp_status)
+{
+ float64 fp64 = float32_to_float64(in, fp_status);
+ return conv_df_to_4u(fp64, fp_status);
+}
+
+int64_t conv_sf_to_8s(float32 in, float_status *fp_status)
+{
+ float64 fp64 = float32_to_float64(in, fp_status);
+ return conv_df_to_8s(fp64, fp_status);
+}
+
+int32_t conv_sf_to_4s(float32 in, float_status *fp_status)
+{
+ float64 fp64 = float32_to_float64(in, fp_status);
+ return conv_df_to_4s(fp64, fp_status);
+}
--
2.7.4
- [RFC PATCH v5 09/33] Hexagon (target/hexagon) architecture types, (continued)
- [RFC PATCH v5 09/33] Hexagon (target/hexagon) architecture types, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 10/33] Hexagon (target/hexagon) instruction and packet types, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 14/33] Hexagon (target/hexagon) instruction printing, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 11/33] Hexagon (target/hexagon) register fields, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 13/33] Hexagon (target/hexagon) instruction/packet decode, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 15/33] Hexagon (target/hexagon/arch.[ch]) utility functions, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 12/33] Hexagon (target/hexagon) instruction attributes, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 17/33] Hexagon (target/hexagon/fma_emu.[ch]) utility functions, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 20/33] Hexagon (target/hexagon) generator phase 2 - generate header files, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 08/33] Hexagon (target/hexagon) GDB Stub, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 16/33] Hexagon (target/hexagon/conv_emu.[ch]) utility functions,
Taylor Simpson <=
- [RFC PATCH v5 21/33] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 07/33] Hexagon (target/hexagon) scalar core helpers, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 25/33] Hexagon (target/hexagon) instruction classes, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 31/33] Hexagon (tests/tcg/hexagon) TCG tests, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 18/33] Hexagon (target/hexagon/imported) arch import, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 19/33] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 23/33] Hexagon (target/hexagon) opcode data structures, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 22/33] Hexagon (target/hexagon) generater phase 4 - decode tree, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 24/33] Hexagon (target/hexagon) macros, Taylor Simpson, 2020/10/29
- [RFC PATCH v5 26/33] Hexagon (target/hexagon) TCG generation, Taylor Simpson, 2020/10/29