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[PATCH v5 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
From: |
Alexey Baturo |
Subject: |
[PATCH v5 6/6] [RISCV_PM] Allow experimental J-ext to be turned on |
Date: |
Thu, 22 Oct 2020 10:43:09 +0300 |
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1c00d9ea26..56633c14eb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -465,6 +465,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (cpu->cfg.ext_j) {
env->mmte |= PM_EXT_INITIAL;
+ target_misa |= RVJ;
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
--
2.20.1
- [PATCH v5 0/6] RISC-V Pointer Masking implementation, Alexey Baturo, 2020/10/22
- [PATCH v5 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2020/10/22
- [PATCH v5 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode, Alexey Baturo, 2020/10/22
- [PATCH v5 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2020/10/22
- [PATCH v5 1/6] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2020/10/22
- [PATCH v5 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2020/10/22
- [PATCH v5 6/6] [RISCV_PM] Allow experimental J-ext to be turned on,
Alexey Baturo <=
- Re: [PATCH v5 0/6] RISC-V Pointer Masking implementation, no-reply, 2020/10/22