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[PULL 31/44] hw/mips/malta: Fix FPGA I/O region size
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 31/44] hw/mips/malta: Fix FPGA I/O region size |
Date: |
Sat, 17 Oct 2020 16:02:30 +0200 |
The FPGA present on the CoreCard has an I/O region 1MiB wide.
Refs:
- Atlas User’s Manual (Document Number: MD00005)
- Malta User’s Manual (Document Number: MD00048)
Fixes: ea85df72b60 ("mips_malta: convert to memory API")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200905213049.761949-1-f4bug@amsat.org>
---
hw/mips/malta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 1e2b750719e..a4a4c386268 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -578,7 +578,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion
*address_space,
memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
&s->iomem, 0, 0x900);
memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
- &s->iomem, 0xa00, 0x10000 - 0xa00);
+ &s->iomem, 0xa00, 0x100000 - 0xa00);
memory_region_add_subregion(address_space, base, &s->iomem_lo);
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
--
2.26.2
- [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper, (continued)
- [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 24/44] hw/mips/mipssim: Correct CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 25/44] hw/mips/jazz: Correct CPU frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 26/44] hw/mips/cps: Expose input clock and connect it to CPU cores, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 29/44] hw/mips/cps: Do not allow use without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 30/44] target/mips/cpu: Display warning when CPU is used without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 31/44] hw/mips/malta: Fix FPGA I/O region size,
Philippe Mathieu-Daudé <=
- [PULL 32/44] hw/mips/malta: Move gt64120 related code together, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 33/44] hw/mips/malta: Use clearer qdev style, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 34/44] hw/mips: Simplify loading 64-bit ELF kernels, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 35/44] hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 36/44] hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 37/44] hw/mips: Remove exit(1) in case of missing ROM, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 38/44] tests/acceptance: Add MIPS record/replay tests, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 39/44] docs/system: Update MIPS CPU documentation, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 40/44] MAINTAINERS: Remove myself, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 41/44] MAINTAINERS: Put myself forward for MIPS target, Philippe Mathieu-Daudé, 2020/10/17